73S1209F Data Sheet
DS_1209F_004
Interrupt Priority 0 Register (IP0): 0xA9 Å 0x00
Table 46: The IP0 Register
MSB
LSB
IP0.0
–
WDTS
IP0.5
IP0.4
IP0.3
IP0.2
IP0.1
Bit
Symbol
Function
IP0.6
WDTS
Watchdog timer status flag. Set when the watchdog timer has expired.
The internal reset will be generated, but this bit will not be cleared by the
reset. This allows the user program to determine if the watchdog timer
caused the reset to occur and respond accordingly. Can be read and
cleared by software.
Note: The remaining bits in the IP0 register are not used for watchdog control.
Watchdog Timer Reload Register (WDTREL): 0x86 Å 0x00
Table 47: The WDTREL Register
MSB
LSB
WDPSEL WDREL6 WDREL5 WDREL4 WDREL3 WDREL2 WDREL1 WDREL0
Bit
Symbol
Function
Prescaler select bit. When set, the watchdog is clocked through an
additional divide-by-16 prescaler.
WDTREL.7
WDPSEL
WDTREL.6
to
WDTREL.0
Seven bit reload value for the high-byte of the watchdog timer. This
WDREL6-0 value is loaded to the WDT when a refresh is triggered by a
consecutive setting of bits WDT and SWDT.
48
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
