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73S1209F-68IMR/F 参数 Datasheet PDF下载

73S1209F-68IMR/F图片预览
型号: 73S1209F-68IMR/F
PDF下载: 下载PDF文件 查看货源
内容描述: 自包含的密码键盘,智能卡读卡器IC的UART至ISO7816 / EMV桥接IC [Self-Contained PINpad, Smart Card Reader IC UART to ISO7816 / EMV Bridge IC]
分类和应用:
文件页数/大小: 123 页 / 1421 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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DS_1209F_004  
73S1209F Data Sheet  
1.7.3.1 Interrupt Overview  
When an interrupt occurs, the MPU will vector to the predetermined address as shown in Table 32. Once  
the interrupt service has begun, it can only be interrupted by a higher priority interrupt. The interrupt  
service is terminated by a return from the RETI instruction. When a RETI is performed, the processor will  
return to the instruction that would have been next when the interrupt occurred.  
When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is  
set regardless of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per  
machine cycle, then samples are polled by the hardware. If the sample indicates a pending interrupt  
when the interrupt is enabled, then the interrupt request flag is set. On the next instruction cycle, the  
interrupt will be acknowledged by hardware forcing an LCALL to the appropriate vector address.  
Interrupt response will require a varying amount of time depending on the state of the MPU when the  
interrupt occurs. If the MPU is performing an interrupt service with equal or greater priority, the new  
interrupt will not be invoked. In other cases, the response time depends on the current instruction. The  
fastest possible response to an interrupt is 7 machine cycles. This includes one machine cycle for  
detecting the interrupt and six cycles to perform the LCALL.  
1.7.3.2 Special Function Registers for Interrupts  
Interrupt Enable 0 Register (IEN0): 0xA8 Å 0x00  
Table 19: The IEN0 Register  
MSB  
EAL  
LSB  
EX0  
WDT  
ES0  
ET1  
EX1  
ET0  
Bit  
Symbol  
EAL  
WDT  
Function  
IEN0.7  
IEN0.6  
IEN0.5  
IEN0.4  
IEN0.3  
IEN0.2  
IEN0.1  
IEN0.0  
EAL = 0 – disable all interrupts.  
Not used for interrupt control.  
ES0  
ET1  
EX1  
ET0  
EX0  
ES0 = 0 – disable serial channel 0 interrupt.  
ET1 = 0 – disable timer 1 overflow interrupt.  
EX1 = 0 – disable external interrupt 1.  
ET0 = 0 – disable timer 0 overflow interrupt.  
EX0 = 0 – disable external interrupt 0.  
Rev. 1.2  
33