73S1209F Data Sheet
DS_1209F_004
1.7.3 Interrupts
The 80515 core provides 10 interrupt sources with four priority levels. Each source has its own request
flag(s) located in a special function register (TCON, IRCON, and SCON). Each interrupt requested by the
corresponding flag can be individually enabled or disabled by the enable bits in SFRs IEN0, IEN1, and
IEN2. Some of the 10 sources are multiplexed in order to expand the number of interrupt sources.
These will be described in more detail in the respective sections.
External interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of
the 73S1209F, for example the USR I/O, smart card interface, analog comparators, etc. The external
interrupt configuration is shown in Figure 8.
PDMUXCtl
Clear PWRDN bit
USR0
USR1
t0
USR2
USR
USR
0
1
int0
USR
Int
USR3
USR4
USR5
USR6
USR7
USR
Pads
USR
Int
Int
Ctl
Int
Ctl
Ctl
Ctl
t1
int1
+
Delay
int2
int3
INT2
INT3
INT
Pads
Card_Det
VCC_OK
CRDCtl
Wait Timeout
Card Event
VCC_TMR
RxData
+
+
SCInt
SCIE
int4
TX_Event
Tx_Sent
TX_Error
RX_Error
MPU
CORE
VccCTL
During STOP, IDLE
when PWRDN bit is set
INT5
Ctl
KeyPad
int5
int6
2
I C
INT6
Ctl
VDD_Fault
Analog
Comp
Serial
Ch 0
SerChan 0 int
SerChan 1 int
Serial
Ch 1
Figure 8: External Interrupt Configuration
32
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
