DS_1209F_004
73S1209F Data Sheet
The master clock control register enables different sections of the clock circuitry and specifies the value
of the VCO Mcount divider. The MCLK must be configured to operate at 96MHz to ensure proper
operation of some of the peripheral blocks according to the following formula:
MCLK = (Mcount * 2 + 4) * FXTAL = 96MHz
Mcount is configured in the MCLKCtl register must be bound between a value of 1 to 7. The possible
crystal or external clock frequencies for getting MCLK = 96MHz are shown in Table 11.
Table 11: Frequencies and Mcount Values for MCLK = 96MHz
F
XTAL (MHz)
12.00
9.60
Mcount (N)
2
3
4
5
6
8.00
6.86
6.00
Master Clock Control Register (MCLKCtl): 0x8F Å 0x0A
Table 12: The MCLKCtl Register
MSB
LSB
MCT.2 MCT.1 MCT.0
HSOEN KBEN SCEN
–
–
Bit
Symbol
Function
High-speed oscillator disable. When set = 1, disables the high-speed crystal
oscillator and VCO/PLL system. Do not set this bit = 1.
MCLKCtl.7
HSOEN
MCLKCtl.6
MCLKCtl.5
MCLKCtl.4
MCLKCtl.3
MCLKCtl.2
MCLKCtl.1
KBEN
SCEN
–
1 = Disable the keypad logic clock.
1 = Disable the smart card logic clock.
–
MCT.2
MCT.1
This value determines the ratio of the VCO frequency (MCLK) to the high-
speed crystal oscillator frequency such that:
MCLK = (MCount*2 + 4)* FXTAL. The default value is MCount = 2h such that
MCLK = (2*2 + 4)*12.00MHz = 96MHz.
MCLKCtl.0
MCT.0
The MPU clock that drives the CPU core defaults to 3.6923MHz after reset. The MPU clock is scalable
by configuring the MPU Clock Control register.
Rev. 1.2
25
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
