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73S1209F-68IMR/F 参数 Datasheet PDF下载

73S1209F-68IMR/F图片预览
型号: 73S1209F-68IMR/F
PDF下载: 下载PDF文件 查看货源
内容描述: 自包含的密码键盘,智能卡读卡器IC的UART至ISO7816 / EMV桥接IC [Self-Contained PINpad, Smart Card Reader IC UART to ISO7816 / EMV Bridge IC]
分类和应用:
文件页数/大小: 123 页 / 1421 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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73S1209F Data Sheet  
DS_1209F_004  
Program Status Word (PSW):  
Table 9: PSW Register Flags  
MSB  
LSB  
CV  
AC  
F0  
RS1  
RS  
OV  
P
Bit  
Symbol  
CV  
Function  
PSW.7  
PSW.6  
PSW.5  
PSW.4  
Carry flag.  
AC  
Auxiliary Carry flag for BCD operations.  
General purpose Flag 0 available for user.  
F0  
RS1  
Register bank select control bits. The contents of RS1 and RS0 select  
the working register bank:  
RS1/RS0  
Bank Selected  
Bank 0  
Location  
00  
01  
10  
11  
(0x00 – 0x07)  
(0x08 – 0x0F)  
(0x10 – 0x17)  
(0x18 – 0x1F)  
PSW.3  
RS0  
Bank 1  
Bank 2  
Bank 3  
PSW.2  
PSW.1  
PSW.0  
OV  
F1  
P
Overflow flag.  
General purpose Flag 1 available for user.  
Parity flag, affected by hardware to indicate odd / even number of “one”  
bits in the Accumulator, i.e. even parity.  
Stack Pointer (SP): The stack pointer is a 1-byte register initialized to 0x07 after reset. This register is  
incremented before PUSH and CALL instructions, causing the stack to begin at location 0x08.  
Data Pointer: The data pointer (DPTR) is 2 bytes wide. The lower part is DPL, and the highest is DPH.  
It can be loaded as a 2-byte register (MOV DPTR,#data16) or as two registers (e.g. MOV DPL,#data8). It  
is generally used to access external code or data space (e.g. MOVC A,@A+DPTR or MOVX A,@DPTR  
respectively).  
Program Counter: The program counter (PC) is 2 bytes wide initialized to 0x0000 after reset. This  
register is incremented during the fetching operation code or when operating on data from program  
memory. Note: The program counter is not mapped to the SFR area.  
Port Registers: The I/O ports are controlled by Special Function Registers USR70 and USR8. The  
contents of the SFR can be observed on corresponding pins on the chip. Writing a 1 to any of the ports  
(see Table 10) causes the corresponding pin to be at high level (3.3V), and writing a 0 causes the  
corresponding pin to be held at low level (GND). The data direction registers UDIR70 and UDIR8 define  
individual pins as input or output pins (see the User (USR) Ports section for details).  
22  
Rev. 1.2