73S1209F Data Sheet
FEATURES
80515 Core:
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1 clock cycle per instruction (most instructions)
CPU clocked up to 24MHz
32kB Flash memory with security
2kB XRAM (User Data Memory)
256 byte IRAM
Hardware watchdog timer
Communication Interfaces:
DS_1209F_004
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Full-duplex serial interface (1200bps to
115kbps UART)
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I
2
C Master Interface (400kbps)
Man-Machine Interface and I/Os:
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5x6 Keyboard (hardware scanning,
debouncing and scrambling)
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(9) User I/Os
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Up to 2 programmable current outputs (LED)
Voltage Detection:
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Analog Input (detection range: 1.0V to 2.5V)
Operating Voltage:
2.7V to 3.6V Digital power supply
4.75 to 5.5V Analog, smart card power
supply
Oscillators:
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Single low-cost 6MHz to 12MHz crystal
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An Internal PLL provides all the necessary clocks
to each block of the system
Interrupts:
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Standard 80C515 4-priority level structure
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9 different sources of interrupt to the core
Power Down Modes:
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2 standard 80C515 Power Down and IDLE
modes
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Extensive device power down mode
Timers:
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(2) Standard 80C52 timers T0 and T1
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(1) 16-bit timer
Built-in ISO-7816 Card Interface:
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Linear regulator produces VCC for the card
(1.8V, 3V or 5V)
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Full compliance with EMV 4.1
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Activation/Deactivation sequencers
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Auxiliary I/O lines (C4 and C8 signals)
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7kV ESD protection on all interface pins
Communication with Smart Cards:
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ISO-7816 UART for protocols T=0, T=1
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(2) 2-Byte FIFOs for transmit and receive
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Configured to drive multiple external Teridian
73S8010x interfaces (for multi-SAM
architectures)
Operating Temperature:
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-40°C to 85°C
Package:
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68-pin QFN, 44-pin QFN
Software:
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Turnkey firmware:
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Compliant with PC/SC, CCID, ISO7816
and EMV4.1 specifications
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Features a Power Down mode accessible
form the host
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Supports Plug & Play over serial interface
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Windows® XP driver available (*)
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Windows CE / Mobile driver available (*)
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Linux and other OS: Upon request
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Or for custom developments:
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A complete set of ISO-7816, EMV4.1 and
low-level libraries are available for T=0 /
T=1
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Two-level Application Programming
Interface (ANSI C-language libraries)
(*) Contact Teridian Semiconductor for
conditions and availability
2
Rev. 1.2