DS_1209F_004
73S1209F Data Sheet
RESET
ANA_IN
TEST
TCLK
ISBR
RXTX
ERST
GND
TBUS3
ICE INTERFACE
VDD
VDD
PLL
and
TIMEBASES
TBUS2
TBUS0
TBUS1
SEC
VDD
VOLTAGE REFERENCE
AND FUSE TRIM
CIRCUITRY
VPD REGULATOR
VCC
CONTROL
LOGIC
VPC
VCC
GND
RST
X12IN
X12OUT
12MHz
OSCILLATOR
CLK
SMART CARD LOGIC
ISO UART and CLOCK GENERATOR
SMART
CARD
ISO
INTERFACE
I/O
AUX1
AUX2
OCDSI
GND
FLASH/ROM
PROGRAM
MEMORY
32KB
MEMORY_
CONTROL
CONTROL
UNIT
ROW0
ROW1
ROW2
ROW3
ROW4
ROW5
COL0
COL1
COL2
COL3
COL4
RAM_
SFR_
CONTROL
TIMER_0_
1
PRES
PRESB
EXTERNAL
SMART
CARD
INTERFACE
KEYPAD
INTERFACE
FLASH
INTERFACE
SCRATCH
IRAM
256B
ALU
CORE
SCLK
SIO
DATA
XRAM
2KB
PMU
WATCH-
DOG
TIMER
INT2
ISR
INT3
PORTS
SERIAL
USR0
USR1
USR2
USR3
USR4
USR5
USR6
USR7
USR8
I
2
C
MASTER
INT.
USR(8:0)
DRIVERS
GND
RXD
TXD
SCL
SDA
PERIPHERAL
INTERFACE
and SFR LOGIC
LED
DRIVERS
Pins only avaiable on 68 pin package.
Figure 1: IC Functional Block Diagram
Rev. 1.2
LED1
LED0
Pins avaiable on both 68 and 44 pin packages.
7
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
