73S1209F Data Sheet
DS_1209F_004
The mass erase sequence is:
1. Write 1 to the FLSH_MEEN bit in the FLSHCTL register (SFR address 0xB2[1]).
2. Write pattern 0xAA to ERASE (SFR address 0x94).
Note: The mass erase cycle can only be initiated when the ICE port is enabled.
The page erase sequence is:
1. Write the page address to PGADDR (SFR address 0xB7[7:1])
2. Write pattern 0x55 to ERASE (SFR address 0x94)
The PGADDR register denotes the page address for page erase. The page size is 512 (200h) bytes and
there are 128 pages within the flash memory. The PGADDR denotes the upper seven bits of the flash
memory address such that bit 7:1 of the PGADDR corresponds to bit 15:9 of the flash memory address.
Bit 0 of the PGADDR is not used and is ignored. The MPU may write to the flash memory. This is one of
the non-volatile storage options available to the user. The FLSHCTL SFR bit FLSH_PWE (flash program
write enable) differentiates 80515 data store instructions (MOVX@DPTR,A) between Flash and XRAM
writes. Before setting FLSH_PWE, all interrupts need to be disabled by setting EAL = 1. Table 3 shows
the location and description of the 73S1209F flash-specific SFRs.
Any flash modifications must set the CPUCLK to operate at 3.6923 MHz (MPUCLKCtl = 0x0C)
before any flash memory operations are executed to insure the proper timing when modifying the
flash memory.
12
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
