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73S1209F-68IM/F 参数 Datasheet PDF下载

73S1209F-68IM/F图片预览
型号: 73S1209F-68IM/F
PDF下载: 下载PDF文件 查看货源
内容描述: 自包含的密码键盘,智能卡读卡器IC的UART至ISO7816 / EMV桥接IC [Self-Contained PINpad, Smart Card Reader IC UART to ISO7816 / EMV Bridge IC]
分类和应用: 电源电路电源管理电路
文件页数/大小: 123 页 / 1421 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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73S1209F Data Sheet  
DS_1209F_004  
1.7.13.1 ISO 7816 UART  
An embedded ISO 7816 (hardware) UART is provided to control communications between a smart card  
and the 73S1209F MPU. The UART can be shared between the one built-in ICC interface and the  
external ICC interface. Selection of the desired interface is made by register SCSel. Control of the  
external interface is handled by the I2C interface for any external 8010 devices. The following is a list of  
features for the ISO 7816 UART:  
Two-byte FIFO for temporary data storage on both TX and Rx data.  
Parity checking in T=0. This feature can be enabled/disabled by firmware. Parity error reporting to  
firmware and Break generation to ICC can be controlled independently.  
Parity error generation for test purposes.  
Retransmission of last byte if ICC indicates T=0 parity error. This feature can be enabled/disabled by  
firmware.  
Deletion of last byte received if ICC indicates T=0 parity error. This feature can be enabled/disabled  
by firmware.  
CRC/LRC generation and checking. CRC/LRC is automatically inserted into T=1 data stream by the  
hardware. This feature can be enabled/disabled by firmware.  
Support baud rates: 230000, 115200, 57600, 38400, 28800, 19200, 14400, 9600 under firmware  
control (assuming 12MHz crystal) with various F/D settings  
Firmware manages F/D. All F/D combinations are supported in which F/D is directly divisible by 31 or  
32 (i.e. F/D is a multiple of either 31 or 32).  
Flexible ETU clock generation and control.  
Detection of convention (direct or indirect) character TS. This affects both polarity and order of bits in  
byte. Convention can be overridden by firmware.  
Supports WTX Timeout with an expanded Wait Time Counter (28 bits).  
A Bypass Mode is provided to bypass the hardware UART in order for the software to emulate the  
UART (for non-standard operating modes). In such a case, the I/O line value is reflected in SFR  
SCCtl or SCECtl respectively for the built-in or external interfaces. This mode is appropriate for  
some synchronous and non T=0 / T=1 cards.  
The single integrated smart card UART is capable of supporting T=0 and T=1 cards in hardware  
therefore offloading the bit manipulation tasks from the firmware. The embedded firmware instructs the  
hardware which smart card it should communicate with at any point in time. Firmware reconfigures the  
UART as required when switching between smart cards. When the 73S1209F has transmitted a  
message with an expected response, the firmware should not switch the UART to another smart card  
until the first smart card has responded. If the smart card responds while another smart card is selected,  
that first smart card’s response will be ignored.  
70  
Rev. 1.2  
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