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73S1209F-44IM/F 参数 Datasheet PDF下载

73S1209F-44IM/F图片预览
型号: 73S1209F-44IM/F
PDF下载: 下载PDF文件 查看货源
内容描述: 自包含的密码键盘,智能卡读卡器IC的UART至ISO7816 / EMV桥接IC [Self-Contained PINpad, Smart Card Reader IC UART to ISO7816 / EMV Bridge IC]
分类和应用: 电源电路电源管理电路PC
文件页数/大小: 123 页 / 1421 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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DS_1209F_004  
73S1209F Data Sheet  
1.7.2 Power Control Modes  
The 73S1209F contains circuitry to disable portions of the device and place it into lower power standby  
modes. This is accomplished by either shutting off the power or disabling the clock going to the block.  
The miscellaneous control registers MISCtl0, MISCtl1 and the Master Clock Control register (MCLKCtl)  
provide control over the power modes. There is also a device power down mode that will stop the core,  
clock subsystem and the peripherals connected to it. The PWRDN bit in MISCtl0 will setup the  
73S1209F for power down and disable all clocks. The power down mode should only be initiated by  
setting the PWRDN bit in the MISCtl0 register and not by manipulating individual control bits in various  
registers. Figure 5 shows how the PWRDN bit controls the various functions that comprise power down  
state.  
Note: the PWRDN Signal is not the direct version of the PWRDN Bit. There are delays from assertion of the  
PWRDN bit to the assertion of the PWRDN Signal (32 MPU clocks) Refer to the Power Down sequence diagram.  
PWRDN Signal  
MISCtl0 - PWRDN  
Analog functions  
(VCO, PLL,  
reference and bias  
circuits, etc.)  
VDDFCtl - VDDFEN  
VDDFAULT  
+
ACOMP - CMPEN  
ANALOG  
COMPARE  
+
+
High Speed OSC  
Smart Card Power  
MCLCKCtl - HOSEN  
+
+
SCVCCCtl - SCPRDN  
MISCtl1 - FRPEN  
Flash Read Pulse  
one-shot circuit  
These are the  
block references.  
These are the registers and  
the names of the control bits.  
Figure 5: Power-Down Control  
When the PWRDN bit is set, the clock subsystem will provide a delay of 32 MPUCLK cycles to allow the  
program to set the STOP bit in the PCON register. This delay will enable the program to properly halt the  
core before the analog circuits shut down (high speed oscillator, VCO/PLL, voltage reference and bias  
circuitry, etc.). The PDMUX bit in SFR INT5Ctl should be set prior to setting the PWRDN bit in order to  
configure the wake up interrupt logic. The power down mode is de-asserted by any of the interrupts  
connected to external interrupts 0, 4 and 5 (external USR[0:7], smart card and Keypad). These interrupt  
sources are OR’ed together and routed through some delay logic into INT0 to provide this functionality.  
The interrupt will turn on the power to all sections that were shut off and start the clock subsystem. After  
the clock subsystem clocks start running, the MPUCLK begins to clock a 512 count delay counter. When  
the counter times out, the interrupt will then be active on INT0 and the program can resume. Figure 6  
shows the detailed logic for waking up the 73S1209F from a power down state using these specific  
interrupt sources. Figure 7 shows the timing associated with the power down mode.  
Rev. 1.2  
27