73S1121F
EMV Smart-Card Terminal Controller
with Built-in Dual ISO-7816 Interface and USB
DATA SHEET
Pin
Total
Number
Pins
128 TQFP
Pin Name
Type
Description
ALE
PSEN
EA
RD
WR
42
41
45
47
46
49
52
55
58
62
67
71
76
51
54
57
60
61
64
66
69
70
74
75
78
79
80
82
83
1
1
1
1
1
O
O
I
I/O
I/O
Address latch enable. A pulse for latching the low byte of the address
on the AD pins during access to external memory. ALE is internally
used to demultiplex the low address byte A(7:0)
Program store enable. This output goes low during a fetch from
program external memory. Active low
External Access enable. When this pin is low, the core fetches code
from external program memory only
Read. A strobe, active during an external read. To be used as a read
enable for external data memory devices. Active low.
Write. A strobe, active during an external write. To be used as a read
enable for external data memory devices. Active low
AD(7)
AD(6)
AD(5)
AD(4)
AD(3)
AD(2)
AD(1)
AD(0)
A(15)
A(14)
A(13)
A(12)
A(11)
A(10)
A(9)
A(8)
A(7)
A(6)
A(5)
A(4)
A(3)
A(2)
A(1)
A(0)
8
I/O
Multiplexed Low-byte Address bus / 8-bit Data BUS.
Address/Data. The low byte of the address and the data byte time
multiplexed during external memory accesses.
There is no need to use this bus to extract the low-address byte, since it
is already demultiplexed and available on the pins A7:0
16
O
Address pins; address during external memory accesses.
A(7:0) are generated internally by demultiplexing of AD(7:0) with ALE
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©
2005 TERIDIAN Semiconductor Corporation
Rev 2.3
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
