73S1121F
EMV Smart-Card Terminal Controller
with Built-in Dual ISO-7816 Interface and USB
DATA SHEET
Pin
Total
Number
Pins
128 TQFP
20
Pin Name
Type
Description
LCDDAT (3)
LCDDAT (2)
LCDDAT (1)
LCDDAT (0)
LCD_Enable
(LCDDAT (4))
LCD_RW
(LCDDAT (5))
LCD_RS
(LCDDAT (6))
ANA_IN (5)
ANA_IN (4)
ANA_IN (3)
VREF
VBG
RESET
ISP_Program
N/C
Reserved
PROM_Program
19
18
17
21
22
23
3
2
1
128
127
40
38
7; 12; 43;
44; 89;
121; 122
120
4
I/O
LCD driver dedicated I/O lines - Data pins.
Can be used as standard I/Os
LCD driver dedicated I/O line: LCD Enable. Can be used as standard
I/O
LCD driver dedicated I/O line: LCD Read/Write. Can be used as
standard I/O
LCD driver dedicated I/O line: LCD Register Select. Can be used as
standard I/O
Analog Inputs - (Voltage detection inputs 0.2V to 2.5V
±
3%)
Voltage reference. 2.5V
±
7%. Decouple with 0.1
µ
F capacitor to VNA.
Bandgap output - internal use. To be decoupled with 0.1
µ
F capacitor to
VNA. Nothing else should be connected to VBG
73S1121F Reset. Active high
Forces internal Flash programming in ISP mode at reset. Active High.
Inactive Low, suitable for normal operation. Internal pull-down allows NC
for normal operation
Not Connected
To be connected to VND
Forces internal Flash programming in PROM parallel mode at reset.
Active High. Internal pull-down allows NC for normal operation
Digital security inputs that control the internal protection fuses. Active
High. Internal pull-down allows NC for normal operation
00 – Inactive.
01- Permanently deactivates both PROM programming mode,
TERIDIAN testing modes.
10 – Permanently deactivates the external interface of address and data
signals to the processor
11- Permanently deactivates the ISP programming mode.
Any combination of the 3 protection modes can be achieved by applying
the proper sequence on these pins
1
1
1
3
1
1
1
1
5
2
1
I/O
I/O
I/O
I
O
O
I
I
-
-
I
SEC1
4
2
I
SEC2
5
Page: 7 of 25
©
2005 TERIDIAN Semiconductor Corporation
Rev 2.3
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
