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73M2901CE-IGV/F 参数 Datasheet PDF下载

73M2901CE-IGV/F图片预览
型号: 73M2901CE-IGV/F
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片调制解调器 [Single Chip Modem]
分类和应用: 调制解调器电信集成电路电信电路
文件页数/大小: 22 页 / 266 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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73M2901CE Data Sheet  
DS_2901CE_031  
6 Design Considerations  
The 73M2901CE single chip modem includes all the basic modem functions. Programmable configuration  
options make this device highly adaptable to a wide variety of applications.  
Unlike digital logic circuitry, modem designs must contend with precise frequency tolerances and verify  
low-level analog signals to ensure acceptable performance. Using good analog circuit design practices  
will generally result in a sound design. The crystal oscillator should be held to a 50 ppm tolerance. The  
recommendations in this section should be taken into consideration when starting new designs.  
6.1 Layout Considerations  
Good analog/digital design rules must be used to control system noise in order to obtain high  
performance in modem designs. The more digital circuitry present in the application, the more attention  
to noise control is needed.  
High speed, digital devices should be locally bypassed, and the telephone line interface and the modem  
should be located next to each other near where the telephone line connection is accessed. It is  
recommended that power supplies and ground traces be routed separately to the analog and digital portions  
on the board. Digital signals should not be routed near low-level or high impedance analog traces.  
The 73M2901CE should be considered a high performance analog device. A 3.3 µF electrolytic capacitor in  
parallel with a 0.1 µF Ceramic capacitor should be placed between each VPD and VND pin and a 10 µF and  
0.1 µF between VPA and VNA. A 0.1 µF ceramic capacitor should be placed between VREF and VNA as  
well as between VBG and VNA. Use of ground planes and large traces on power is recommended.  
6.2 73M2901CE Design Compatibility  
The Teridian 73M2901CE is an enhanced version of the Teridian 73M2901CL and has a number of  
additional features. These parts are highly compatible with the earlier 73M2901, however, users should  
pay special attention when changing an existing 73M2901 design to use the 73M2901CE or 73M2901CL.  
From a hardware standpoint, the key differences involve the User I/O pins USR10 and USR11, the  
ASRCH pin and the HBDEN pin. An additional user I/O pin, USR20, replaces the ASRCH pin on the  
73M2901CE. This pin may remain safely connected to TXD as long as the host software does not  
reconfigure USR20 as an output (S104 bit0=0).  
The 73M2901CE contains a high efficiency low power hybrid driver. Due to this enhancement, HBDEN is no  
longer required. This pin is an internal no-connect and can safely remain connected to its previous VPD or  
GND. The functions of USR10 and USR11 are related to Caller ID and Line In Use/Parallel Pickup support.  
Software enhancements to the 73M2901CE are typically achieved by the addition of new AT commands.  
The device can be considered a superset of the 73M2901CL and 73M2901C. When converting a design to  
the 73M2901CE, it is recommended that the user check the commands and register settings for backward  
compatibility to the earlier parts (refer to the 73M2901CE AT Command User Guide for complete details).  
6.3 Telephone Line Interface  
Transmit levels at the line are dependent on the interface used between the pins and the line. The internal  
hybrid line drivers eliminate the need for additional active circuitry to drive the line-coupling transformer.  
The analog outputs TXAP and TXAN can be connected directly to the transformer (with the required  
impedance matching series resistor or network). Depending upon transformer design (specifically dry  
transformers), operation may be affected by the limited amount of DC current generated by the analog  
outputs (DC offset). For this reason, Teridian recommends using a coupling capacitor with those  
transformers to insure maximum performance.  
The line interface circuits shown in Section 7 Reference Designs represent the basic components and  
values for interfacing the Teridian 73M2901CE analog pins to the telephone line. The values of these  
components have been calculated to minimize the transmission and reception path hybrid losses and are  
linked by the following equation: R15=0.242 x R13.  
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Rev. 3.3