73M1822/73M1922 Data Sheet
DS_1x22_001
Pin
Pin Name
Number
Type
Description
Crystal oscillator circuit input pin.
14
OSCIN/MCLK
I
Input from an external clock source. Crystal frequency range
supported is 9 MHz – 27 MHz.
15
16
17
18
19
20
OSCOUT
VNA/VNPLL
VNA
O
Crystal oscillator output pin. (N.C. with external oscillator)
Negative PLL ground
GND
GND
O
Negative analog ground
Call progress audio output
AOUT
VPA/VPM
VNM/VNT
PWR
GND
Positive analog supply
Negative transformer supply
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
M/S
I
Master or slave selection / reset - active during transition
S/Sh regulator sense
SRE
SRB
VBG
ACS
VNS
VPS
RXP
RXM
TXM
DCD
DCS
DCG
DCI
I
O
S/Sh regulator drive
O
VBG bypass, connect to 0.1uF capacitor to VPS
AC current sense
I
GND
LIC analog/digital negative ground
LIC analog/digital positive supply voltage
Receive plus -signal input
PWR
I
I
Receive minus - signal input
Transmit minus - signal output
DCD for integrated Darlington
DC loop current sense
O
O
I
O
DC loop drive
I
DC loop input
RGM
RGP
OFH
M20BP
VND/VNX
SCP
MID
I
I
Ring minus voltage input
Ring plus voltage input
O
Off-hook control
I
Substrate connection. Connect to VNX.
LIC digital/analog negative ground
Positive side of the secondary pulse transformer winding
Charge pump -normally left open
LIC supply from the barrier side
GND
I/O
I/O
PWR
VPX
2.6 Exposed Bottom Pad on 73M1x66B QFN Packages
The 73M1822 and 73M1922 QFN packages have exposed pads on the underside that are intended
for device manufacturing purposes. These exposed pads are not intended for thermal relief (heat
dissipation) and should not be soldered to the PCB. Soldering of the exposed pad could also
compromise electrical isolation/insulation requirements for proper voltage isolation. Avoid any PCB
traces or through-hole vias on the PCB beneath the exposed pad area.
16
Rev. 1.6
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
