DS_1903_032
73M1903 Data Sheet
Table 10: Clock Generation Register Settings for Fxtal = 24.000 MHz
Reg Address
Ichp
Kvco
[2:0]
Fs (kHz)
7.2
8h
DA
02
9h Ah Bh Ch Dh* (μA)
EF 30 15 1A C4
2C 31 13 10 C4
10
10
0
1
8.0
2.4*8/7*3
=8.22857142858
08
72 41 1C 3E C5
12
1
8.4
9.0
9.6
DA
08
EF 41 19 10 C4
66 11 0A 1E C4
EF 42 1C 1E C4
12
6
1
1
2
DA
12
2.4*10/7*3
=10.2857142857
DA
3E
EF 43 1E 7E C6
A9 33 14 76 C6
12
10
3
3
2.4*8/7*4
=10.9714285714
11.2
12
DA
08
EF 53 21 1A C4
66 14 0E 14 C4
EF 45 26 14 C4
14
6
3
4
5
12.8
DA
12
2.4*10/7*4
=13.7142857143
10
54
8C 46 20 80 C7
CA 46 1C 3E C5
12
12
6
6
14.4
Table 11: Clock Generation Register Settings for Fxtal = 25.35 MHz
Reg Address
Ichp Kvco
9h Ah Bh Ch Dh* (μA) [2:0]
FS (KHz)
8h
7.2
92
F4 50 1A 06 C2
14
0
FrcVco
0
1
System
Clock
2
Loop Filter Control
VCO Locked
Xtal Oscillator
Up
Kd
NCO
Prescaler
Fref
Fvco
R1
VCO
Kvco
Charge
Pump
Fxtal
C2
PFD
C1
Dn
Ichp Control
2
Kvco Control
2
NCO
Figure 5: Clock Generation
Rev. 2.0
17
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
