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73M1903 参数 Datasheet PDF下载

73M1903图片预览
型号: 73M1903
PDF下载: 下载PDF文件 查看货源
内容描述: 调制解调器模拟前端 [Modem Analog Front End]
分类和应用: 调制解调器
文件页数/大小: 46 页 / 530 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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DS_1903_032  
73M1903 Data Sheet  
3 Clock Generation  
3.1 Crystal Oscillator and Pre-scaler NCO  
The crystal oscillator operates over wide choice of crystals (from 9 MHz to 27 MHz) and it is first input to  
an NCO based pre-scaler (divider) prior to being passed onto an on-chip PLL. The intent of the pre-  
scaler is to convert the crystal oscillator frequency, Fxtal, to a convenient frequency to be used as a  
reference frequency, Fref, for the PLL. The NCO pre-scaler requires a set of three numbers to be  
entered through the serial port (Pseq[7:0], Prst[2:0] and Pdvsr[2:0]. The PLL also requires 3 numbers as  
for programming; Ndvsr[6:0], Nseq[7:0], and Nrst[2:0]. The following is a brief description of the registers  
that control the NCOs, PLLs, and sample rates for the 73M1903 IC. The tables show some examples of  
the register settings for different clock and sample rates. A more detailed discussion on how these values  
are derived can be found in Appendix B.  
3.1.1 Control Register (CTRL 8): Address 08h  
Reset State 00h  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Pseq7  
Pseq6  
Pseq5  
Pseq4  
Pseq3  
Pseq2  
Pseq1  
Pseq0  
This corresponds to the sequence of divisor. If Prst{2:0] =0 this register is ignored.  
3.1.2 Control Register (CTRL 9): Address 09h  
Reset State 0Ah  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Prst2  
Prst1  
Prst0  
Pdvsr4  
Pdvsr3  
Pdvsr2  
Pdvsr1  
Pdvsr0  
Prst[2:0] represents the rate at which the sequence register is reset.  
Pdvsr[4:0] represents the divisor.  
3.1.3 Control Register (CTRL 10): Address 0Ah  
Reset State 22h  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
FL  
Bit 2  
Bit 1  
Bit 0  
Ichp3  
Ichp2  
Ichp1  
Ichp0  
Kvco2  
Kvco1  
Kvco0  
Kvco2:0 represents the magnitude of Kvco associated with the VCO within PLL. This indicates the center  
frequency of the VCO when the control voltage is 1.6 Volts and the slope of the VCO freq versus control  
voltage (i.e., Kvco.). FL represents the PLL loop filter settings.  
Table 4: Kvco versus Settings at Vc=1.6 V, 25 °C  
Kvco2  
Kvco1  
Kvco0  
Fvco  
Kvco  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
33 MHz  
36 MHz  
44 MHz  
48 MHz  
57 MHz  
61 MHz  
69 MHz  
73 MHz  
38 MHz/v  
38 MHz/v  
40 MHz/v  
40 MHz/v  
63 MHz/v  
63 MHz/v  
69 MHz/v  
69 MHz/v  
Rev. 2.0  
13