DS_1903_032
73M1903 Data Sheet
6
Test Modes
There are two loop back test modes that affect the configuration of the analog front end. The internal
loop back mode connects the serial bit stream generated by the analog receiver to the input of the analog
transmitter. This loop back mode is similar to a remote analog loop back mode and can be used to
evaluate the operation of the analog circuits. When using this loop back mode, the TXAN/TXAP pins
should not be externally coupled to the RXAP/RXAN pins. Set bit 4 (INTLB) in register 1h (CTRL2) to
enter this loop back mode.
The second loop back test mode is the external loop back mode, or local analog loop back mode. In this
mode, the analog transmitter outputs are fed back into the input of the analog receiver. Set bit 5 (ANALB)
in register 1h (CTRL2) to enter this loop back mode. In this mode, TBS must be kept to below a value
that corresponds to less than 1.16 V/2.31 V x -6 dB = 25% of the full scale code of +/- 32768 at TXD in
order to ensure that the receiver is not overdriven beyond the maximum of 1.16 Vpkpk diff for Rxg=11(0
dB) setting. See Table 18 for the maximum allowed transmit levels. Check the transmitted data against
received data via serial interface. This tests the functionality of essentially all blocks, both digital and
analog, of the chip.
There is a third loopback mode that bypasses the analog circuits entirely. Digital loop back forces the
transmitter digital serial bit stream (from DSDM) to be routed into the digital receiver’s sinc3 filters. Set bit
6 (DIGLB) in register 1h (CTRL2) to enter this loop back mode.
7
Power Saving Modes
The 73M1903 has only one power conservation mode. When the ENFE, bit 7 in register 0h, is zero the
clocks to the filters and the analog are turned off. The transmit pins output a nominal 80 kΩ impedance.
The clock to the serial port is running and the GPIO and other registers can be read or updated.
Rev. 2.0
25
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
