73M1903C
Modem Analog Front End
DATA SHEET
frame after enabling FSD must be Data. For the two daisy chained devices, the data/control frames are
32 bits. The first 16 bits go to the first device; the next 16 bits go to the second device in the chain, as
timed by FSD of the first device. For four daisy-chained devices, the data/control frames are 64 bits. The
first 16 bits go to the first device in the chain; the next 16 bits go to the second device in the chain as
started by FSD of the first device, etc. FSD is always ”Late Type” frame sync.
Up to eight 73M1903C devices may be daisy-chained if the control frame sync is placed at the middle of
the data frame sync interval. Four devices may be daisy-chained if the control frame sync is placed at the
1/4 of the data frame sync interval. In all cases involving slave and daisy chain operation, only hardware
controlled Control Frames can be supported. Software requested control frames are not allowed.
In slave mode the relationship of Fs and Fsclk is Fsclk/Fs, with a range of from 96 to 256 SCLKs per Fs.
Again, the host controls the relationship of FS to SCLK, with the condition that Fsclk>750kHz and
Fsys=4608*Fs. The 79M1903C PLL must be programmed to generate Fsys with those conditions. To
program the 73M1903C NCOs, OSCIN (Fsclk)=SCLK=Fref when Pdvsr=1 and Prst=0 in the calculations.
Fsys in the previous discussion is Fvco in the calculations which is equal to 4608*Fs. For example, two
typical cases are Fsclk=256*Fs and Fsclk=144*Fs.
For the case when Fsclk=256*Fs and Fs=8kHz, the 79M1903C PLL has to be set to
Fsys=4608*Fs=36.864MHz, and Sclk=256*8kHz=2.048MHz. Therefore Ndvsr=36.864/2.048=18 (12h)
and Nrst=0
For the case when Fsclk=144*Fs and d Fs=8kHz, the 79M1903C PLL has to be set to
Fsys=4608*Fs=36.864MHz and Sclk=144*8kHZ=1.152MHz. Therefore Ndvsr=36.864/1.152=32 (20h)
and Nrst=0
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© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 4.3
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