DS_1x66B_001
73M1866B/73M1966B Data Sheet
9.6 Line-Side Device Operating Modes
The architecture of the 73M1x66B is unique in that the isolation barrier device, an inexpensive pulse
transformer, is used to provide power and also bidirectional data between the Host-Side Device and the
Line-Side Device. When the 73M1x66B is on hook, all the power for the Line-Side Device is provided
over the barrier interface. After the Line-Side Device goes off hook, the telco line supplies approximately
8 mA to the Line-Side Device while the host provides the remainder across the barrier. It is also possible
to power the Line-Side Device entirely from the line provided there is at least 17 mA of loop current
available. Setting the ENLPW bit enables this mode and turns off the power supplied across the barrier.
There is a penalty in using this mode in that the noise and dynamic range are about 6 dB worse than with
the Barrier Powered Mode. It is therefore recommended that the Line Powered Mode be reserved for
applications where the absolute minimum power from the host side is a priority and the reduction in
performance can be tolerated.
Figure 32 shows the AC and DC circuits of the Line-Side Device.
TP14
OFH
3
OHS
DCI
1
Q7
MMBTA42
1
2
2 4
1
Q6
BCP-56
+
C4
10uF
R58 240
U2
3
2
3
Q4
1
20
19
18
17
16
15
14
13
12
11
1
MMBTA92
4
3
DCI
DCG
DCS
DCD
TXM
RXM
RXP
VPS
VNS
ACS
VBG
2
3
RGN
RGP
OFH
VNX
SCP
MID
DCD
TXM
RXM
RXP
R12
5.1K
BR1
3
1
4
R3
412K, 1%
HD04
+
-
2
5
Q3
1
6
MMBTA42
7
2
8
R65 200
VPX
SRE
SRB
9
10
73M1916-20
R11
5.1K
R4
100K, 1%
R5 8.2
3
SRB
SRE
1
Q5
MMBTA06
2
Figure 32: Line-Side Device AC and DC Circuits
The DCIV bits control the voltage versus current characteristics of the 73M1x66B by monitoring the
voltage at the line divided down by the ratios of (R3+R4)/R4 (5:1) measured at the DCI pin. This voltage
does not include the voltage across the Q4 and the bridge. When both the ENAC and ENDC bits are set
(the hold mode), the DCIV characteristics follow approximately a 50 Ω load line offset by a factor
determined by the DCIV bits. If ENDC=1 and ENAC=0, the 73M1x66B will go into the ”Seize state mode”
and the DC voltage load characteristic will be reduced to meet the Australian seize voltage requirements
regardless of the setting of the DCIV bits.
9.7 Fail-Safe Operation of Line-Side Device
The 73M1x66B provides additional protection against improper operation during error and harmful
external events. These include power or communication failure with the Line-Side Device and the
detection of abnormal voltages and currents on the line. The basis of this protection is to ensure that
under these conditions the device is in the On-Hook state and the isolation is provided.
The following events will cause the 73M1x66 Line-Side Device to go to the On-Hook state if it is Off-Hook:
1. A Power-On Reset occurs while Off-Hook.
2. The non-transition timer function (see DISNTR) is triggered by the absence of any signal transitions
for more than 400 µs on the barrier interface, indicating a problem with communications.
3. The power supply to the Line-Side Device is below normal operating levels.
Rev. 1.6
63
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
