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73M1866B-IM/F 参数 Datasheet PDF下载

73M1866B-IM/F图片预览
型号: 73M1866B-IM/F
PDF下载: 下载PDF文件 查看货源
内容描述: [Consumer Circuit, ROHS COMPLIANT, QFN-42]
分类和应用: 商用集成电路
文件页数/大小: 88 页 / 1139 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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DS_1x66B_001  
73M1866B/73M1966B Data Sheet  
Upon power up, the following sequence should be used to ensure barrier synchronization:  
1. The 73M1906B starts in Barrier Powered Mode and transmits a preamble to aid the PLL locking of  
the Line-Side Device.  
2. When PLL Lock detect is achieved the Line-Side Device transmits status data to the Host-Side  
Device.  
3. When the Line-Side status Data is detected by the Host-Side Device, the barrier is considered to be  
in synchronization by the Host-Side Device.  
4. If the auto-poll mode is enabled, the Device ID is transmitted, which is followed by transmit data.  
5. Upon detection of the Device ID, the Line-Side Device considers the barrier to be in synchronization  
in host-to-line side direction.  
6. The Line-Side Device starts sending Receive Data.  
7. If the Auto-Poll bit is enabled, the Host-Side Device will have polled the Device ID of the Line-Side  
Device. If the barrier is synchronized, then Register 1Dh, bits 7-4, will be 1101. If not synchronized,  
then 0000.  
9.4 Auto-Poll  
Once the Barrier Interface acquires synchronization, the Barrier Interface state machine automatically  
sends a polling command to Line-Side Device requesting it to return its Device ID. This is provided in  
REV. Upon power up or loss of barrier synchronization, the contents of REV is cleared. After the  
auto-poll sequence, the host should read REV. A non-zero value indicates that synchronization is  
established.  
The auto-poll mechanism is disabled by resetting the ENAPOL control bit.  
9.5 Barrier Control Functions  
Table 37: Barrier Control Functions  
Function  
Mnemonic Location  
Register  
Type  
Description  
DISNTR  
0x15[6]  
WO Disable No-Transition Timer  
If enabled, the No-Transition Timer is a safety feature. If the barrier  
fails, i.e. no transition is detected for 400 μs, the Line-Side Device  
resets itself and goes on hook to prevent line holding in a failure  
condition.  
0 = Enables No-Transition Timer of 400 μs. (Default)  
1 = Disables No-Transition Timer.  
ENAPOL  
ENLPW  
0x05[3]  
0x02[2]  
W
W
Enable Automatic Polling  
0 = Disables automatic polling.  
1 = Initiates automatic polling of the 73M1x66B Device ID upon the  
establishment of the barrier SYN. (Default)  
If SYN is lost, the Device ID will be reset to 0000.  
Enable Line Power  
0 = Barrier Powered Mode is selected. (Default)  
1 = Line Powered Mode is selected.  
Bit ENLVD must have the value of 0 before switching from Line  
Powered Mode to Barrier Powered Mode. Otherwise level  
detection is disabled and the transition to Barrier Powered Mode  
will not occur.  
ENSYNL  
Rev. 1.6  
0x05[1]  
W
Enable Synch Loss Detection Interrupt  
0 = Disables Synch Loss Detection Interrupt.  
1 = Enables Synch Loss Detection Interrupt. (Default) When the  
73M1x66B detects a loss of synchronization in Host-Side Barrier  
Interface, SYNL 0x03[1] will be set and reset when read.  
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