73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A
Single-Chip Modem
DATA SHEET
REGISTER DESCRIPTIONS
Eight 8-bit internal registers are accessible for
control and status monitoring. The registers are
accessed in read or write operations by addressing
the A0, A1 and A2 address lines in Serial mode, or
the AD0, AD1 and AD2 lines in Parallel mode. The
address lines are latched by ALE. Register CR0
controls the method by which data is transferred
over the phone line. CR1 controls the interface
between the microprocessor and the 73K324L
internal state. DR is a detect register which provides
an indication of monitored modem status conditions.
TR, the tone control register, controls the DTMF
generator, answer, guard tones, SCT, calling tone,
and RXD output gate used in the modem initial
connect sequence. CR2 is the primary DSP control
interface and CR3 controls transmit attenuation and
receive gain adjustments. All registers are read/write
except for DR and ID, which are read only. Register
control and status bits are identified below:
REGISTER BIT SUMMARY
ADDRESS
REGISTER
CONTROL
REGISTER
0
CONTROL
REGISTER
1
DETECT
REGISTER
AD - A0
D7
MODULATION
OPTION
TRANSMIT
PATTERN
1
RECEIVE
LEVEL
RXD
OUTPUT
CONTROL
D6
MODULATION
TYPE
1
TRANSMIT
PATTERN
0
PATTERN
S1 DET
TRANSMIT
GUARD TONE/
SCT/CALLING
TONE
SPECIAL
REGISTER
ACCESS
TRISTATE
TX/RXCLK
D5
MODULATION
TYPE
0
ENABLE
DETECT
INTERRUPT
RECEIVE
DATA
TRANSMIT
ANSWER
TONE
DATA BIT NUMBER
D4
TRANSMIT
MODE
2
BYPASS
SCRAMBLER/
ADD PH. EQ.
(V.23)
UNSCR.
MARK
DETECT
TRANSMIT
DTMF
D3
TRANSMIT
MODE
1
CLK
CONTROL
D2
TRANSMIT
MODE
0
D1
TRANSMIT
ENABLE
D0
ANSWER/
ORIGINATE
CR0
000
CR1
001
RESET
TEST
MODE
1
CALL
PROGRESS
DETECT
DTMF1/
OVERSPEED
TEST
MODE
0
SIGNAL
QUALITY
DTMF0/GUARD/
ANSWER/
CALLING/SCT
DR
010
CARRIER
DETECT
SPECIAL
TONE
DETECT
DTMF2/
4 WIRE FDX
TONE
CONTROL
REGISTER
CONTROL
REGISTER
2
CONTROL
REGISTER
3
SPECIAL
REGISTER
TR
011
DTMF3
CR2
100
0
CALL
INITIALIZE
TRANSMIT
S1
RECEIVE
GAIN
BOOST
16 WAY
RESET
DSP
TRANSMIT
ATTEN.
2
SQ
SELECT 1
TRAIN
INHIBIT
TRANSMIT
ATTEN.
1
SQ
SELECT 0
EQUALIZER
ENABLE
TRANSMIT
ATTEN.
0
CR3
101
TXDALT
0
TRANSMIT
ATTEN.
3
TXD
SOURCE
SR
101
0
TX BAUD
CLOCK
RX UNSCR.
DATA
0
0
ID
REGISTER
ID
110
1
1
1
0
X
X
X
X
NOTE: When a register containing reserved control bits is written into, the reserved bits must be programmed as
0's.
X = Undefined, mask in software.
Page: 6 of 30
©
2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
