73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A
Single-Chip Modem
DATA SHEET
ASYNCHRONOUS MODE
The Asynchronous mode is used for communication
with asynchronous terminals which may transfer
data at 600, 1200, or 2400 bit/s +1%, -2.5% even
though the modem’s output is limited to the nominal
bit rate ±0.01% in DPSK and QAM modes. When
transmitting in this mode the serial data on the TXD
input is passed through a rate converter which
inserts or deletes stop bits in the serial bit stream in
order to output a signal that is the nominal bit rate
±0.01%. This signal is then routed to a data
scrambler and into the analog modulator where di-bit
or quad-bit encoding results in the output signal.
Both the rate converter and scrambler can be
bypassed for handshaking and synchronous
operation as selected. Received data is processed
in a similar fashion except that the rate converter
now acts to reinsert any deleted stop bits and output
data to the terminal at no greater than the bit rate
plus 1%. An incoming break signal (low through two
characters) will be recognized and passed through
without incorrectly inserting a stop bit.
The SYNC/ASYNC converter has an extended
Overspeed mode, which allows selection of an
output speed range of either +1% or +2.3%. In the
extended Overspeed mode, some stop bits are
output at 7/8 the normal width.
Both the SYNC/ASYNC rate converter and the data
descrambler are automatically bypassed in the FSK
modes.
SYNCHRONOUS MODE
Synchronous operation is possible only in the QAM
or DPSK modes. Operation is similar to that of the
Asynchronous mode except that data must be
synchronized to a clock and no variation in data
transfer rate is allowable. Serial input data appearing
at TXD must be valid on the rising edge of TXCLK.
TXCLK is an internally derived 1200 or 2400 Hz
signal in Internal mode and is connected internally to
the RXCLK pin in Slave mode. Receive data at the
RXD pin is clocked out on the falling edge of
RXCLK. The asynch/synch converter is bypassed
when Synchronous mode is selected and data is
transmitted out at essentially the same rate as it is
input.
PARALLEL CONTROL INTERFACE
Eight 8-bit registers are provided for control, option
select, and status monitoring. These registers are
addressed with the AD0, AD1, and AD2 multiplexed
address lines (latched by ALE) and appear to a
control microprocessor as seven consecutive
memory locations. Six control registers are
read/write. The detect and ID registers are read only
and cannot be modified except by modem response
to monitored parameters.
SERIAL CONTROL INTERFACE
The Serial Command mode allows access to the
73K324L control and status registers via a serial
control port. In this mode the A0, A1, and A2 lines
provide register addresses for data passed through
the DATA pin under control of the
RD
and
WR
lines.
A read operation is initiated when the
RD
line is
taken low. The next eight cycles of EXCLK will then
transfer out eight bits of the selected address
location LSB first. A write takes place by shifting in
eight bits of data LSB first for eight consecutive
cycles of EXCLK.
WR
is then pulsed low and data
transfer into the selected register occurs on the
rising edge of
WR.
TONE GENERATOR
The DTMF generator controls the sending of the
sixteen standard DTMF tone pairs. The tone pair
sent is determined by selecting TRANSMIT DTMF
(bit D4) and the 4 DTMF bits (D0-D3) of the TONE
register. Transmission of DTMF tones from TXA is
gated by the TRANSMIT ENABLE bit of CR0 (bit D1)
as with all other analog signals.
FULL DUPLEX OPERATION
Four-wire full duplex operation is allowed in all
modes. This feature allows transmission and
reception in the same band for four wire applications
only.
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©
2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
