73K324BL
CCITT V.22bis,V.23,V.22,V.21, Bell 212A
Single-Chip Modem w/ Integrated Hybrid
DATA SHEET
TIMING DIAGRAMS
TLL
ALE
TLC
TLA
TRW
TCL
RD
TLC
TWW
TDW
WR
TRD
TRDF
TWD
TAL
AD0-AD7
ADDRESS
READ DATA
ADDRESS
WRITE DATA
CS
FIGURE 2: Bus Timing Diagram (Parallel Control Mode)
EXCLK
RD
TAC
TCA
ADDRESS
TRD
D0
AD0-AD2
DATA
TRDF
TCKD
D1
D2
D3
D4
D5
D6
D7
FIGURE 3: Read Timing Diagram (Serial Control Mode)
EXCLK
TWW
WR
TCKW
TAC
TCA
AD0-AD2
DATA
ADDRESS
TWH
TDCK
D0
D1
D2
D3
D4
D5
D6
D7
FIGURE 4: Write Timing Diagram (Serial Control Mode)
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© 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 6.1