73K224L
V.22bis, V.22, V.21, Bell 212A, 103
Single-Chip Modem
DATA SHEET
TIMING DIAGRAMS
BUS TIMING DIAGRAM (PARALLEL CONTROL MODE)
TLL
ALE
TLC
TRW
TCL
RD
TLC
TWW
WR
TLA
TRD
TRDF
TWD
TAL
ADDRESS
TDW
WRITE DATA
READ DATA
ADDRESS
AD0-AD7
CS
READ TIMING DIAGRAM (SERIAL CONTROL MODE )
T1
T2
EXCLK
TRCLK
RD
TAR
TRA
ADDRESS
A0-A2
TRD
D0
TRDF
TCKDR
D2
D1
D3
D4
D5
D6
D7
DATA
WRITE TIMING DIAGRAM (SERIAL CONTROL MODE)
T2
EXCLK
T1
TWW
WR
TCKW
TAW
TWA
A0-A2
ADDRESS
TCKDW
TDCK
D0
D1
D2
D3
D4
D5
D6
D7
DATA
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© 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1