73K224L
V.22bis, V.22, V.21, Bell 212A, 103
Single-Chip Modem
DATA SHEET
DYNAMIC CHARACTERISTICS AND TIMING (continued)
Timing (Refer to Timing Diagrams)
PARAMETER
Parallel Mode
TAL
CONDITION
MIN
NOM
MAX
UNIT
CS/Addr. setup before ALE Low
CS/Addr. hold after ALE Low
ALE Low to RD/WR Low
RD/WR Control to ALE High
Data out from RD Low
ALE width
30
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TLA
TLC
40
10
TCL
TRD
90
40
TLL
25
TRDF
TRW
Data float after RD High
RD width
70
70
70
20
TWW
WR width
TDW
Data setup before WR High
Data hold after WR High
TWD
Serial Mode
TRCK
TAR
Clock High after RD Low
Address setup before RD Low
Address hold after RD Low
RD to Data valid
250
0
T1
ns
ns
ns
ns
ns
ns
TRA
350
TRD
300
40
TRDF
TCKDR
Data float after RD High
Read Data out after Falling Edge of
EXCLK
300
TWW
TAW
TWA
WR width
350
50
ns
ns
ns
Address setup before WR Low
Address hold after Rising Edge of
50
WR
TCKDW
TCKW
TDCK
Write Data hold after Falling Edge
of EXCLK
200
330
50
ns
ns
ns
ns
WR High after Falling Edge of
EXCLK
T1 +
T2
Data setup before Falling Edge of
EXCLK
T1, T2
Minimum Period
500
NOTE: T1 and T2 are the low/high periods, respectively, of EXCLK in serial mode.
NOTE: Asserting ALE, CS, and RD or WR concurrently can cause unintentional register accesses. When using
non-8031 compatible processors, care must be taken to prevent this from occurring when designing the
interface logic.
Page: 23 of 31
© 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
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