73K224BL
V.22bis, V.22, V.21, Bell 212A, 103
Single-Chip Modem w/ Integrated Hybrid
DATA SHEET
ELECTRICAL SPECIFICATIONS (continued)
DYNAMIC CHARACTERISTICS AND TIMING
(TA = -40°C to +85°C, VDD = recommended range unless otherwise noted.)
PARAMETER
CONDITION
MIN
NOM
MAX
UNIT
QAM/DPSK Modulator
Carrier suppression
Output Amplitude
Measured at TXA
35
dB
TX Scrambled marks
ATT = 0100 (default)
-11.5
-10
-9
dBm0
FSK Modulator/Demodulator
Output Frequency Error
Transmit Level
CLK = 11.0592 MHz
-0.31
-11.5
+0.20
-9
%
ATT = 0100 (default)
-10
dBm0
transmit dotting pattern
TXA output distortion
All products through BPF
-45
dB
%
Output bias distortion
@ RXD
Dotting pattern measured at RXD
receive level -20 dBm, SNR 20 dB
-10
+10
Output jitter @ RXD
Integrated for 5 seconds
Integrated for 5 seconds
-15
-17
+15
+17
%
%
Sum of bias distortion and
output jitter
Answer Tone Generator (2100 or 2225 Hz)
Output amplitude
ATT = 0100 (default level)
-11.5
-10
-9
dBm0
dB
Not in V.21
Output Distortion
DTMF Generator
Frequency accuracy
Output amplitude
Output amplitude
Twist
Distortion products in receive band
Not in V.21
-40
-0.03
-10
-8
+0.25
-8
%
Low band, ATT = 0100, DPSK mode
High band, ATT = 0100, DPSK mode
High band to low band, DPSK mode
Refer to performance curves
In call init mode
dBm0
dBm0
dB
-6
1
2
3
Receiver Dynamic Range
Call Progress Detector
Detect level
-43
-3
dBm0
460 Hz test signal
-34
0
dBm0
dBm0
ms
Reject level
460 Hz test signal
-40
25
25
Delay time
-70 dBm0 to -30 dBm0 step
-30 dBm0 to -70 dBm0 step
Hold time
ms
Page: 23 of 33
© 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
