73K222BL
V.22, V.21, Bell 212A, 103 Single-Chip
Modem with Integrated Hybrid
DATA SHEET
TIMING DIAGRAMS
TLL
ALE
TLC
TRW
TCL
RD
TLC
TWW
WR
TLA
TRD
TRDF
TWD
TAL
ADDRESS
TDW
WRITE
READ DATA
ADDRESS
AD0-AD7
CS
FIGURE 2: Bus Timing Diagram
EXCLK
RD
TAC
TCA
ADDRESS
A0-A2
DATA
TRDF
TRD
TCKD
D0
D1
D2
D3
D4
D5
D6
D7
FIGURE 3: Read Timing Diagram (Serial Version)
EXCLK
TWW
WR
TCKW
TAC
TCA
ADDRESS
A0-A2
DATA
TWH
TDCK
D0
D1
D2
D3
D4
D5
D6
D7
FIGURE 4: Write Timing Diagram (Serial Version)
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© 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.2