73K222BL
V.22, V.21, Bell 212A, 103 Single-Chip
Modem with Integrated Hybrid
DATA SHEET
DYNAMIC CHARACTERISTICS AND TIMING (continued)
PARAMETER
CONDITION
MIN
NOM
MAX
UNIT
GUARD TONE GENERATOR
Tone Accuracy
550 Hz
1800 Hz
550 Hz
1800 Hz
550 Hz
1800 Hz
-20
-4.0
-7.0
+20
-2.0
-5.0
-50
Hz
dB
dB
dB
dB
Tone Level
(Below DPSK Output)
-3.0
-6.0
Harmonic Distortion
700 to 2900 Hz
-60
TIMING (Refer to Timing Diagrams)
TAL
CS/Address setup before ALE Low
12
0
ns
ns
TLA
CS CS hold after ALE low
ADD Address hold after ALE Low
ALE Low to RD/WR Low
RD/WR Control to ALE High
Data out from RD Low
ALE width
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TLC
TCL
TRD
TLL
0
70
50
15
TRDF
TRW
TWW
TDW
TWD
Data float after RD High
RD width
50
50
15
12
WR width
Data setup before WR High
Data hold after WR High
TCKD
Data out after EXCLK Low
WR after EXCLK Low
200
ns
ns
ns
ns
ns
TCKW (serial mode)
TDCK (serial mode)
TAC (serial mode)
TCA (serial mode)
TWH (serial mode)
150
150
50
Data setup before EXCLK Low
Address setup before control*
Address hold after control*
Data Hold after EXCLK
50
20
* Control for setup is the falling edge of RD or WR. Control for hold is the falling edge of RD or the rising edge
of WR.
NOTE: Asserting ALE, CS, and RD or WR concurrently can cause unintentional register accesses. When using
non-8031 compatible processors, care must be taken to prevent this from occurring when designing the
interface logic.
Page: 19 of 26
© 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
