FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
Description
Name
Location
Reset Wake
Dir
IEN_WD_NROVF 20B0[0]
0
0
R/W Active high watchdog near overflow interrupt enable.
IE_XFER
IE_RTC
SFR E8[0]
SFR E8[1]
0
0
0
0
Interrupt flags. These flags monitor the XFER_BUSY interrupt and the RTC_1SEC
interrupt. The flags are set by hardware and clear automatically.
R/W
Indicates that the MPU was awakened by the autowake timer. This bit is typically read
by the MPU on bootup. The firmware must write a zero to this bit to clear it.
IE_WAKE
SFR E8[5]
0
–
–
R/W
Interrupt inputs. The MPU may read these bits to see the status of external interrupts
R/W INT0, INT1 up to INT6. These bits do not have any memory and are primarily intended
for debug use.
INTBITS
SFR F8[6:0]
2023
–
L
L
L
L
L
L
LCD_BITMAP
[31:24]
0
0
0
0
0
0
R/W Configuration for DIO11/SEG31 through DIO4/SEG24. Unused bits should be set to zero.
1 = LCD pin, 0 = DIO pin. Check Table 54 for bit availability.
LCD_BITMAP
[39:32]
2024
R/W Bitmap of DIO19/SEG39 through DIO12/SEG32. Unused bits should be set to zero.
1 = LCD pin, 0 = DIO pin. Check Table 54 for bit availability.
LCD_BITMAP
[55:48]
2026
R/W Bitmap of DIO28/SEG48 through DIO35/SEG55. Unused bits should be set to zero.
1 = LCD pin, 0 = DIO pin. Check Table 54 for bit availability.
LCD_BITMAP
[63:56]
2027
R/W Bitmap of DIO36/SEG56 through DIO43/SEG63. Unused bits should be set to zero.
1 = LCD pin, 0 = DIO pin. Check Table 54 for bit availability.
LCD_BITMAP
[71:64]
2028
R/W Bitmap of DIO44/SEG64 through DIO51/SEG71. Unused bits should be set to zero.
1 = LCD pin, 0 = DIO pin. Check Table 54 for bit availability.
LCD_BLKMAP19 205A[7:4]
R/W
[3:0]
Identifies which segments connected to SEG18 and SEG19 should blink. 1 means
blink. The most significant bit corresponds to COM3, the least significant bit to COM0.
LCD_BLKMAP18 205A[3:0]
[3:0]
Sets the LCD clock frequency for COM/SEG pins (not frame rate) according to the
following (fw = 32768 Hz):
00 = fw/29
R/W
LCD_CLK[1:0]
2021[1:0]
0
L
01 = fw/28
10 = fw/27
11 = fw/26
v1.3
© 2005-2010 TERIDIAN Semiconductor Corporation
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