FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
Description
Name
Location
Reset Wake
Dir
DIO_PV
2008[2]
2008[3]
200F[3]
200F[2]
SFR 9E
SFR 9F
0
0
0
0
0
0
0
0
0
0
0
0
R/W Causes VARPULSE to be output on DIO7.
R/W Causes WPULSE to be output on DIO6.
R/W Causes XPULSE to be output on DIO8.
R/W Causes YPULSE to be output on DIO9.
R/W Serial EEPROM interface data.
DIO_PW
DIO_PX
DIO_PY
EEDATA[7:0]
EECTRL[7:0]
R/W Serial EEPROM interface control.
Emulator clock disable. When ECK_DIS = 1, the emulator clock is disabled.
ECK_DIS
EQU[2:0]
2005[5]
0
0
R/W
If ECK_DIS is set, the emulator and programming devices will be unable to
erase or program the device.
2000[7:5]
0
0
R/W Specifies the power equation to be used by the CE.
EX_XFR
EX_RTC
EX_FWCOL
EX_PLL
2002[0]
2002[1]
2007[4]
2007[5]
0
0
0
0
0
0
0
0
R/W
Interrupt enable bits. These bits enable the XFER_BUSY, the RTC_1SEC, the Firm-
WareCollision (FWCOL) and PLL interrupts. Note that if one of these interrupts is to
be enabled, its corresponding MPU EX enable must also be set. See Section 1.4.9
Interrupts for details.
FIR_LEN[1:0] controls the length of the ADC decimation FIR filter and therefore controls
the time taken for each conversion.
Resulting FIR
Filter Cycles CK32 Cycles
Resulting
Resulting
DC Gain
[M40MHZ, M26MHZ] FIR_LEN[1:0]
[00], [10], or [11]
[01]
00
01
10
00
01
10
138
288
384
186
384
588
1
2
3
1
2
3
0.110017
1.000
FIR_LEN[1:0]
FL_BANK[2:0]
2007[3:2]
1
1
1
1
R/W
2.37037
0.113644
1.000
3.590363
Flash bank. Memory above 32 KB is mapped to the MPU address space from 0x8000
R/W to 0xFFFF in 32 KB banks. When MPU address[15] = 1, the address in flash is
SFR B6[2:0]
mapped to FL_BANK[2:0], MPU Address[14:0]. FL_BANK is reset by the erase cycle.
v1.3
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