FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
3.7
Connecting Three-Wire EEPROMs
µWire EEPROMs and other compatible devices should be connected to the DIO pins DIO4 and DIO5, as
shown in Figure 34 and described below:
•
•
•
•
DIO5 connects to both the DI and DO pins of the three-wire device.
The CS pin must be connected to a vacant DIO pin of the 71M6531.
In order to prevent bus contention, a 10 kΩ to resistor is used to separate the DI and DO signals.
The CS and CLK pins should be pulled down with resistors to prevent operation of the three-wire device
on power-up, before the 71M6531 can establish a stable signal for CS and CLK.
•
The DIO_EEX[1:0] register in I/O RAM must be set to 2 (b10) in order to convert the DIO pins DIO4
and DIO5 to µWire pins.
The µ-Wire EEPROM interface is only functional when MPU_DIV[2:0] = 000.
71M653X
V3P3D
DIO4
EEPROM
VCC
CLK
DI
10 kΩ
DIO5
DIOn
DO
CS
100 kΩ
100 kΩ
Figure 34: Three-Wire EEPROM Connection
3.8
UART0 (TX/RX)
The UART0 RX pin should be pulled down by a 10 kΩ resistor and additionally protected by a 100 pF
ceramic capacitor, as shown in Figure 35.
71M6531D/F, 71M6532D/F
10 kΩ
100 pF
RX
RX
TX
Figure 35: Connections for UART0
TX
3.9
Optical Interface (UART1)
The OPT_TX and OPT_RX pins can be used for a regular serial interface (by connecting a RS-232
transceiver for example), or they can be used to directly operate optical components (for example, an
infrared diode and phototransistor implementing a FLAG interface). Figure 36 shows the basic connections
for UART1. The OPT_TX pin becomes active when the I/O RAM register OPT_TXE is set to 00.
v1.3
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