Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
5.5.5 SPI Slave Port (MISSION Mode)
Table 88: SPI Slave Port (MISSION Mode) Timing
Parameter
Condition
Min
1
Typ
Max
Unit
µs
tSPIcyc PCLK cycle time
tSPILead Enable lead time
tSPILag Enable lag time
15
0
ns
ns
tSPIW
PCLK pulse width:
High
Low
40
40
2
ns
ns
ns
tSPISCK PCSZ to first PCLK fall
Ignore if PCLK is low
when PCSZ falls.
tSPIDIS Disable time
0
ns
ns
ns
ns
tSPIEV PCLK to Data Out
tSPISU Data input setup time
15
10
5
tSPIH
Data input hold time
PCSZ
tSPILead
tSPIcyc
tSPILag
PCLK
tSPIW
tSPIEV
tSPIW
tSPIDIS
tSPISCK
PSDO
PSDI
MSB OUT
LSB OUT
tSPIH
MSB IN
LSB IN
Figure 44: SPI Slave Port (MISSION Mode) Timing
Electrical Specification Footnotes
1. This spec will be guaranteed and verified in production samples, but will not be measured in production.
2. This spec will be guaranteed and verified in production samples, but will be measured in production
only at DC.
3. This spec will be measured in production at the limits of the specified operating temperature.
4. This spec defines a nominal relationship rather than a measured parameter. Correct circuit operation
will be verified with other specs that use this nominal relationship as a reference.
106
© 2005-2010 TERIDIAN Semiconductor Corporation
v1.3
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
