71M6533/71M6534 Data Sheet
FDS_6533_6534_004
FLSH_PWE (flash program write enable) differentiates 80515 data store instructions (MOVX@DPTR,A)
between Flash and XRAM writes. This bit must be cleared by the MPU after each byte write operation.
Write operations to this bit are inhibited when interrupts are enabled.
The MPU cannot write to flash while the CE is executing its code from flash. Two interrupts warn of colli-
sions between the MPU firmware and the CE timing. If a flash write operation is attempted while the CE
is busy, the flash write will not execute and the FW_COL0 interrupt will be issued. If a flash write is still in
progress when the CE would otherwise begin a code pass, the code pass is skipped, the write operation
is completed, and the FW_COL1 interrupt is issued.
The simplest flash write procedure disables the CE during the write operation and interpolates the meter-
ing measurements. However, this results in the loss of at least one second of data, because the CE has
to resynchronize with the mains voltage.
There is a brief guaranteed interval (typically 1/32768 s) between CE executions which occurs 2520 times
per second. The start of the interval can be detected with the CE_BUSY interrupt which occurs on the
falling edge of CE_BUSY (an internal signal measurable from TMUXOUT). However, this guaranteed idle
time (30.5 µs) is too short to write a byte which takes 42 µs or to erase a page of flash memory which
takes at least 20 ms. Some CE code has substantially longer idle times, but in those cases, firmware in-
terrupt latencies can easily consume the available write time. If a flash write fails in this scheme, the fail-
ure can be detected with the FWCOL0 or FWCOL1 interrupt and the write can be retried.
It is practical to pre-erase pages, disable interrupts and poll the CE_BUSY interrupt flag, IRCON[2]. This
method avoids problems with interrupt latency, but can still result in a write failure if the CE code takes
too much time. As mentioned above, polling FWCOL0 and FWCOL1 can detect write failures. However,
the speed in a polling write is only 2520 bytes per second and the firmware cannot respond to interrupts.
As an alternative to using flash, a small EEPROM can store data without compromises. EEPROM inter-
faces are included in the device.
Updating Individual Bytes in Flash Memory
The original state of a flash byte is 0xFF (all ones). Once a value other than 0xFF is written to a flash
memory cell, overwriting with a different value usually requires that the cell be erased first. Since cells
cannot be erased individually, the page has to be copied to RAM, followed by a page erase. After this,
the page can be updated in RAM and then written back to the flash memory.
Flash Erase Procedures
Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper sequence.
These special pattern/sequence requirements prevent inadvertent erasure of the flash memory.
The mass erase sequence is:
1. Write 1 to the FLSH_MEEN bit (SFR address 0xB2[1].
2. Write the pattern 0xAA to FLSH_ERASE (SFR address 0x94).
The mass erase cycle can only be initiated when the ICE port is enabled.
The page erase sequence is:
1. Write the page address to FLSH_PGADR (SFR address 0xB7[7:2].
2. Write the pattern 0x55 to FLSH_ERASE (SFR address 0x94).
Bank-Switching
The program memory of the 71M6533/71M6534 consists of a fixed lower bank of 32 KB, addressable at
0x0000 to 0x7FFF plus an upper banked area of 32 KB, addressable at 0x8000 to 0xFFFF. The I/O RAM
register FL_BANKis used to switch one of four (71M6533/H, 71M6534) or eight (71M6534H) memory banks
of 32 KB each into the address range from 0x8000 to 0xFFFF. Note that when FL_BANK = 0, the upper
bank is the same as the lower bank. Table 38 illustrates the bank switching mechanism.
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