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71M6533H-IGTR/F 参数 Datasheet PDF下载

71M6533H-IGTR/F图片预览
型号: 71M6533H-IGTR/F
PDF下载: 下载PDF文件 查看货源
内容描述: 电能计量IC [Energy Meter IC]
分类和应用:
文件页数/大小: 124 页 / 1997 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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FDS_6533_6534_004  
71M6533/71M6534 Data Sheet  
Address Reset value  
Name  
S1BUF  
Description  
Page  
(Hex)  
(Hex)  
0x9C  
0x00  
Serial Port 1, Data Buffer  
26  
S1RELL  
IEN0  
0x9D  
0xA8  
0xA9  
0xAA  
0xB8  
0xB9  
0xBA  
0xBB  
0xBF  
0xC0  
0xC8  
0xD0  
0xD8  
0xE0  
0xF0  
0x00  
0x00  
0x00  
0xD9  
0x00  
0x00  
0x03  
0x03  
0x00  
0x00  
0x00  
0x00  
0x00  
0x00  
0x00  
Serial Port 1, Reload Register, low byte  
Interrupt Enable Register 0  
26  
31  
34  
26  
31  
34  
26  
26  
20  
32  
32  
23  
26  
23  
23  
IP0  
Interrupt Priority Register 0  
S0RELL  
IEN1  
Serial Port 0, Reload Register, low byte  
Interrupt Enable Register 1  
IP1  
Interrupt Priority Register 1  
S0RELH  
S1RELH  
PDATA  
IRCON  
T2CON  
PSW  
Serial Port 0, Reload Register, high byte  
Serial Port 1, Reload Register, high byte  
High address byte for MOVX@Ri - also called USR2  
Interrupt Request Control Register  
Polarity for INT2 and INT3  
Program Status Word  
WDCON  
A
Baud Rate Control Register (only WDCON[7] bit used)  
Accumulator  
B
B Register  
Accumulator (ACC, A):  
ACC is the accumulator register. Most instructions use the accumulator to hold the operand. The mne-  
monics for accumulator-specific instructions refer to accumulator as A, not ACC.  
B Register:  
The B register is used during multiply and divide instructions. It can also be used as a scratch-pad regis-  
ter to hold temporary data.  
Program Status Word (PSW):  
This register contains various flags and control bits for the selection of the register banks (see Table 11).  
Table 11: PSW Bit Functions (SFR 0xD0)  
PSW Bit  
Symbol Function  
7
6
5
CV  
AC  
F0  
Carry flag.  
Auxiliary Carry flag for BCD operations.  
General purpose Flag 0 available for user.  
F0 is not to be confused with the F0 flag in the CESTATUS register.  
4
3
RS1  
RS0  
Register bank select control bits. The contents of RS1 and RS0 select the  
working register bank:  
RS1/RS0  
00  
Bank selected  
Bank 0  
Location  
0x00 – 0x07  
0x08 – 0x0F  
0x10 – 0x17  
0x18 – 0x1F  
01  
Bank 1  
10  
Bank 2  
11  
Bank 3  
2
1
0
OV  
Overflow flag.  
User defined flag.  
P
Parity flag, affected by hardware to indicate odd or even number of one bits in  
the Accumulator, i.e. even parity.  
v1.1  
© 2007-2009 TERIDIAN Semiconductor Corporation  
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