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71M6533H-IGTR/F 参数 Datasheet PDF下载

71M6533H-IGTR/F图片预览
型号: 71M6533H-IGTR/F
PDF下载: 下载PDF文件 查看货源
内容描述: 电能计量IC [Energy Meter IC]
分类和应用:
文件页数/大小: 124 页 / 1997 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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FDS_6533_6534_004  
71M6533/71M6534 Data Sheet  
Table 4 shows the CE addresses in XRAM allocated to analog inputs from the AFE.  
Table 4: XRAM Locations for ADC Results  
Address (HEX)  
0x00  
Name  
IA  
Description  
Phase A current  
Phase A voltage  
Phase B current  
Phase B voltage  
Phase C current  
Phase C voltage  
Neutral current  
Not used  
0x01  
VA  
0x02  
IB  
0x03  
VB  
0x04  
IC  
0x05  
VC  
ID  
0x06  
0x07 – 0x09  
0x0A  
TEMP  
VBAT  
Temperature  
0x0B  
Battery Voltage  
The CE is aided by support hardware to facilitate implementation of equations, pulse counters, and ac-  
cumulators. This hardware is controlled through I/O RAM locations EQU (equation assist), DIO_PV and  
DIO_PW (pulse count assist), and PRE_SAMPS and SUM_CYCLES (accumulation assist).  
PRE_SAMPS and SUM_CYCLES support a dual-level accumulation scheme where the first accumulator  
accumulates results from PRE_SAMPS samples and the second accumulator accumulates up to  
SUM_CYCLES of the first accumulator results. The integration time for each energy output is  
PRE_SAMPS * SUM_CYCLES/2520.6 (with MUX_DIV = 6). CE hardware issues the XFER_BUSY interrupt  
when the accumulation is complete.  
1.2.10 Meter Equations  
The 71M6533 and 71M6534 provide hardware assistance to the CE in order to support various meter  
equations. This assistance is controlled through I/O RAM location EQU (equation assist). The Compute  
Engine (CE) firmware for industrial configurations can implement the equations listed in Table 5. EQU  
specifies the equation to be used based on the meter configuration and on the number of phases used for  
metering.  
Table 5: Inputs Selected in Regular and Alternate Multiplexer Cycles  
Wh and VARh formula  
Element  
Mux  
Sequence  
ALT Mux Se-  
quence  
EQU Description  
Element 0 Element 1  
2
1 element, 2 W, 1φ with  
neutral current sense  
0
VA · IA  
VA · IB  
N/A  
Sequence is  
programmable programmable  
Sequence is  
with  
SLOTn_SEL  
with  
SLOTn_ALTSEL  
1 element, 3 W, 1φ  
1
2
3
4
5
VA(IA-IB)/2  
VA · IA  
N/A  
N/A  
N/A  
2 element, 3 W, 3φ Delta  
2 element, 4 W, 3φ Delta  
2 element, 4 W, 3φ Wye  
3 element, 4 W, 3φ Wye  
VB · IB  
VC ·IC  
VA(IA-IB)/2  
N/A  
VA(IA-IB)/2 VB(IC-IB)/2  
VA · IA VB · IB  
N/A  
VC · IC  
1.2.11 Real-Time Monitor  
The CE contains a Real-Time Monitor (RTM), which can be programmed to monitor four selectable XRAM  
locations at full sample rate. The four monitored locations are serially output to the TMUXOUT pin via the  
digital output multiplexer at the beginning of each CE code pass. The RTM can be enabled and disabled  
with RTM_E. The RTM output is clocked by CKTEST. Each RTM word is clocked out in 35 cycles and con-  
tains a leading flag bit. See Figure 19 for the RTM output format. RTM is low when not in use.  
v1.1  
© 2007-2009 TERIDIAN Semiconductor Corporation  
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