FDS_6533_6534_004
71M6533/71M6534 Data Sheet
3.8 Connecting Three-Wire EEPROMs
µWire EEPROMs and other compatible devices should be connected to the DIO pins DIO4 and DIO5, as
shown in Figure 35 and described below:
•
•
•
•
DIO5 connects to both the DI and DO pins of the three-wire device.
The CS pin must be connected to a vacant DIO pin of the 71M6533/71M6534.
In order to prevent bus contention, a 10 kΩ to resistor is used to separate the DI and DO signals.
The CS and CLK pins should be pulled down with a resistor to prevent operation of the three-wire
device on power-up, before the 71M6533/71M6534 can establish a stable signal for CS and CLK.
•
The DIO_EEX register in I/O RAM must be set to 2 (b10) in order to convert the DIO pins DIO4 and
DIO5 to µWire pins.
The µ-Wire EEPROM interface is only functional when MPU_DIV[2:0] = 000.
71M6533/71M6534
V3P3D
EEPROM
VCC
DIO4
CLK
DI
10 kΩ
DIO5
DIOn
DO
CS
100 kΩ
100 kΩ
Figure 35: Three-Wire EEPROM Connection
3.9 UART0 (TX/RX)
The UART0 RX pin should be pulled down by a 10 kΩ resistor and additionally protected by a 100 pF ce-
ramic capacitor, as shown in Figure 36.
71M6533/71M6534
10 kΩ
100 pF
RX
RX
TX
Figure 36: Connections for UART0
TX
v1.1
© 2007-2009 TERIDIAN Semiconductor Corporation
69
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
