71M6533/71M6534 Data Sheet
FDS_6533_6534_004
Table 44: TMUX[4:0] Selections
TMUX[4:0]
0
Mode
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
–
Function
DGND
1
Reserved
2
DGND
3
Reserved
4
PLL_2P5
5
Output of the 2.5 V low-power regulator
Internal VBIAS voltage (nominally 1.6V)
Not used
6
7
8 - 0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0X1D
0X1E
0X1F
Reserved
Digital
Digital
–
RTC 1-second output
RTC 4-second output
Not used
Digital
Digital
Digital
Digital
Digital
Digital
Digital
–
V1 comparator output, synchronized to RTCLK
Real-time output from the CE
WDTR_EN (comparator 1 output AND V1LT3)
V2 comparator output (71M6534 only)
V1 comparator output, unsynchronized
RXD (from Optical interface, w/ optional inversion)
MUX_SYNC
Not used
Digital
Digital
Digital
Digital
Digital
CKMPU (MPU clock)
Pulse output
RTCLK (output of the oscillator circuit, nominally 32,786Hz)
CE_BUSY (busy interrupt generated by CE, 396µs)
XFER_BUSY (transfer busy interrupt generated by the CE,
nominally every 999.7ms)
1.4.14 V2 Comparator (71M6534/6534H only)
The 71M6534/6534H offers a pin that is connected to an internal comparator. The voltage applied to this
pin is compared to the internal reference voltage (VBIAS). If the voltage at the V2 pin is above VBIAS,
the comparator output will be high (1). The comparator output is reflected at the TMUXOUT pin, when
0x16 is selected for TMUX[4:0].
52
© 2007-2009 TERIDIAN Semiconductor Corporation
v1.1
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
