FDS_6533_6534_004
71M6533/71M6534 Data Sheet
cal assignment of values for the SLOTn_SEL and SLOTn_ALTSEL registers assuming seven time slots
(MUX_DIV = 7) for the processing of three voltage and current phases plus an additional neutral current.
The correlation between signal numbers, CE memory addresses, and analog signals is given in Table 3.
For the processing of three voltage and current phases in a typical poly-phase meter without neutral
measurement, MUX_DIV is set to 6, and SLOT6_SEL as well as SLOT6_ALTSEL would be empty.
Table 1: Signals Selected for the ADC with SLOTn_SEL and SLOTn_ALTSEL (MUX_DIV = 7)
Regular Slot
Typical Selections
Alternate Slot
Typical Selections
Time Slot
Register
Register
Signal
Signal for
ADC
Signal
Signal for
ADC
Number
Number
0
1
2
3
4
5
6
SLOT0_SEL
SLOT1_SEL
SLOT2_SEL
SLOT3_SEL
SLOT4_SEL
SLOT5_SEL
SLOT6_SEL
SLOT7_SEL
SLOT8_SEL
SLOT9_SEL
0
1
2
3
4
5
6
–
–
–
IA
VA
IB
VB
IC
VC
ID
–
SLOT0_ALTSEL
SLOT1_ALTSEL
SLOT2_ALTSEL
SLOT3_ALTSEL
SLOT4_ALTSEL
SLOT5_ALTSEL
SLOT6_ALTSEL
SLOT7_ALTSEL
SLOT8_ALTSEL
SLOT9_ALTSEL
A
1
B
3
4
5
6
TEMP
VA
VBAT
VB
IC
VC
ID
–
–
The duration of each multiplexer state depends on the number of ADC samples processed by the FIR,
which is set by FIR_LEN. Each multiplexer state will start on the rising edge of CK32. FIR conversions
require 1, 2, or 3 CK32 cycles. The number of CK32 cycles is determined by FIR_LEN.
1.2.3 A/D Converter (ADC)
A single delta-sigma A/D converter digitizes the voltage and current inputs to the 71M6533/71M6534. The
resolution of the ADC is programmable using the I/O RAM registers M40MHZ and M26MHZ (see Table 2).
Table 2: ADC Resolution
Setting for [M40MHZ,
FIR_LEN FIR CE Cycles Resolution
M26MHZ]
[00], [10] or [11]
0
1
2
138
288
384
18 bits
21 bits
22 bits
[01]
0
1
2
186
384
588
19 bits
22 bits
24 bits
Initiation of each ADC conversion is controlled by MUX_CTRL as described above. At the end of each ADC
conversion, the FIR filter output data is stored into the CE RAM location determined by the MUX selection.
1.2.4 FIR Filter
The finite impulse response filter is an integral part of the ADC and it is optimized for use with the multip-
lexer. The purpose of the FIR filter is to decimate the ADC output to the desired resolution. At the end of
each ADC conversion, the output data is stored into the fixed CE RAM location determined by the multip-
lexer selection as shown in Table 3. FIR data is stored LSB justified, but shifted left by eight bits.
v1.1
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TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
