Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
does not require control of the chopping mechanism by the MPU while eliminating the offset for tempera-
ture measurement.
In the second toggle state, CHOP_E = 11, no ALT frame is forced during the last multiplexer cycle in an
accumulation interval and CROSS always toggles near the end of each multiplexer frame.
The internal bias voltage, VBIAS (typically 1.6 V), is used by the ADC when measuring the temperature
and battery monitor signals.
1.2.6 Temperature Sensor
The 71M6531D/F and 71M6532D/F include an on-chip temperature sensor implemented as a bandgap
reference. It is used to determine the die temperature. The MPU may request an alternate multiplexer
cycle containing the temperature sensor output by asserting MUX_ALT.
The primary use of the temperature data is to determine the magnitude of compensation required to offset
the thermal drift in the system (see Section 3.4 Temperature Compensation).
1.2.7 Battery Monitor
The battery voltage is measured by the ADC during alternative multiplexer frames if the BME (Battery
Measure Enable) bit in the I/O RAM is set. While BME is set, an on-chip 45 kΩ load resistor is applied to
the battery and a scaled fraction of the battery voltage is applied to the ADC input. After each alternative
MUX frame, the result of the ADC conversion is available at XRAM address 0x0B. BME is ignored and
assumed zero when system power is not available (V1 < VBIAS). See Section 5.4.4 Battery Monitor.
1.2.8 AFE Functional Description
The AFE functions as a data acquisition system, controlled by the MPU. The main signals (IA, VA, IB and
VB) are sampled, and the ADC counts obtained are stored in XRAM where they can be accessed by the
CE and, if necessary, by the MPU. Alternate multiplexer cycles are initiated less frequently by the MPU to
gather access to the slow temperature and battery signals.
Figure 5 shows the block diagram of the AFE, with current inputs shown only as differential pair of pins
(for the 71M6531D/F, the current input for phase A is a single pin [IA]).
VREF
∆Σ ADC
CONVERTER
VBIAS
VBIAS
FIR
FIR_LEN
IAP
IAN
VADC
22
ADC_E
VREF
MUX
VREF
VA
IBP
IBN
VB
VREF_CAL
VREF_DIS
VBAT
EQU
MUX_ALT
MUX_DIV
TEMP
SENSOR
Figure 5: AFE Block Diagram (Shown for the 71M6532D/F)
14
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
