Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
The duration of each multiplexer state depends on the number of ADC samples processed by the FIR,
which is set by FIR_LEN. Each multiplexer state will start on the rising edge of CK32. The MUX_CTRL
signal sends an FIR_START command to begin the calculation of a sample value from the ADC bit
stream by the FIR. Upon receipt of the FIR_DONE signal from the FIR, the multiplexer will wait until the
next CK32 rising edge to increment its state and initiate the next FIR conversion. FIR conversions require
1, 2, or 3 CK32 cycles. The number of CK32 cycles is determined by FIR_LEN, as shown in Table 2.
1.2.3 A/D Converter (ADC)
A single delta-sigma A/D converter digitizes the voltage and current inputs to the 71M6531D/F and
71M6532D/F. The resolution of the ADC is programmable using the I/O RAM registers M40MHZ and
M26MHZ (see Table 2).
Table 2: ADC Resolution
Setting for [M40MHZ,
M26MHZ]
CK32
Cycles
FIR_LEN
FIR CE Cycles
Resolution
[00], [10] or [11]
0
1
2
1
2
3
138
288
384
18 bits
21 bits
22 bits
[01]
0
1
2
1
2
3
186
384
588
19 bits
22 bits
24 bits
Initiation of each ADC conversion is controlled by MUX_CTRL as described above. At the end of each
ADC conversion, the FIR filter output data is stored into the CE RAM location determined by the MUX
selection.
1.2.4 FIR Filter
The finite impulse response filter is an integral part of the ADC and it is optimized for use with the multip-
lexer. The purpose of the FIR filter is to decimate the ADC output to the desired resolution. At the end of
each ADC conversion, the output data is stored into the fixed CE RAM location determined by the multip-
lexer selection as shown in Table 3. FIR data is stored LSB justified, but shifted left by eight bits.
Table 3: ADC RAM Locations
Address (HEX)
0x00
Name
IA
Address (HEX)
0x09
Name
AUX
0x01
VB
IB
0x0A
TEMP
VBAT
0x02
0x0B
0x03
VA
1.2.5 Voltage References
The device includes an on-chip precision bandgap voltage reference that incorporates auto-zero tech-
niques. The reference is trimmed to minimize errors caused by component mismatch and drift. The re-
sult is a voltage output with a predictable temperature coefficient.
The amplifier within the reference is chopper stabilized, i.e. the polarity can be switched by the MPU us-
ing the I/O RAM register CHOP_E (0x2002[5:4]). The two bits in the CHOP_E register enable the MPU to
operate the chopper circuit in regular or inverted operation, or in toggling mode. When the chopper circuit
is toggled in between multiplexer cycles, DC offsets on the measured signals will automatically be aver-
aged out.
The general topology of a chopped amplifier is shown in Figure 3.
12
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
