Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
1.5.7 Digital I/O – 71M6531D/F
The 71M6531D/F includes up to 22 pins of general-purpose digital I/O. These pins are compatible with 5-
V inputs (no current limiting resistors are needed). The Digital I/O pins can be categorized as follows:
• Dedicated DIO pins (1 pin): PB
• DIO/LCD segment pins (a total of 19 pins):
o
o
o
o
DIO4/SEG24 - DIO15/SEG35 (12 pins)
DIO17/SEG37 (1 pin)
DIO28/SEG48 – DIO29/SEG49 (2 pins)
DIO43/SEG63 - DIO46/SEG66 (4 pins)
• DIO pins combined with other functions (2 pins): DIO2/OPT_TX, DIO1/OPT_RX
The pins DIO4/SEG24 through DIO29/SEG49 are configured by the LCD_MAP DIO registers to be DIO or
segment pins. A one in LCD_MAP defines the pin as a LCD segment output, a zero makes the pin a DIO
pin. Pins configured as LCD pins are controlled with the LCD_SEGnn registers. Pins configured as DIO
can be defined independently as an input or output with the DIO_DIR bits (see Table 41).
Write operations to a disabled DIO are not ignored. Write operations are registered, but do not
affect the pin, or the result of a read operation on the pin, until it becomes a DIO output.
DIO2/OPT_TX will be an active TX output pin at power up (OPT_TXE[1:0] = 00).
A 3-bit configuration word, I/O RAM register DIO_Rx (0x2009[2:0] through 0x200E[6:4], can be used for
certain pins (when configured as DIO) to individually assign an internal resource such as an interrupt or a
timer control (see Table 42 for DIO pins available for this option). This way, DIO pins can be tracked
even if they are configured as outputs.
Table 39 lists the direction registers and configurability associated with each group of DIO pins.
Table 39: Data/Direction Registers and Internal Resources for DIO Pins (71M6531D/F)
–
DIO
PB
1
2
4
5
6
7
8
9
10 11 12 13 14 15
–
–
–
–
–
–
LCD Segment
Pin number
24 25 26 27 28 29 30 31 32 33 34 35
39 40 41 42 43 44 45 46 68 30 21 22
65 60
3
–
–
–
0
1
2
3
4
5
6
7
0
1
2
3
Configuration (DIO
or LCD segment)
LCD_MAP[31:24]
LCD_MAP[31:24] LCD_MAP[39:32]
0
–
1
1
2
–
4
5
6
7
0
1
2
3
4
5
6
7
Data Register
DIO0 = P0 (SFR 0x80)
DIO1 = P1 (SFR 0x90)
2
–
4
5
6
7
0
1
2
3
4
5
6
7
Direction Register
DIO_DIR0 (SFR 0xA2)
DIO_DIR1 (SFR 0x91)
Internal Resources
Configurable
–
–
–
–
–
–
–
–
Y
Y
Y
Y
Y
Y
Y
Y
42
© 2005-2009 TERIDIAN Semiconductor Corporation
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