Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
The MPU clock frequency CKMPU is determined by another divider controlled by the I/O RAM register
MPU_DIV and can be set to MCK/2(MPU_DIV+2) Hz where MPU_DIV varies from 0 to 6. The circuit also ge-
nerates the 2 x CKMPU clock for use by the emulator. The emulator clock is not generated when
ECK_DIS is asserted.
During a power-on reset, [M40MHZ, M26MHZ] defaults to [0,0] and the MCK divider is set to divide by 4.
When [M40MHZ, M26MHZ] = [1,0], the CE clock frequency may be set to 5 MHz or 10 MHz, using the I/O
RAM register CE10MHZ. In this mode, the ADC and FIR clock frequencies remain at 5 MHz. When
[M40MHZ, M26MHZ] = [0,1], the CE, ADC, FIR and MPU clock frequencies are shifted to 6.6 MHz. This
increases the ADC sample rate by 33%. In sleep mode, the M40MHZ and M26MHZ inputs to the clock
generator are forced low.
In brownout mode, the clocks are derived from the crystal oscillator and the clock frequencies are scaled
by 7/8.
1.5.3 Real-Time Clock (RTC)
The RTC is driven directly by the crystal oscillator. It is powered by the net RTC_NV (battery-backed up
supply). The RTC consists of a counter chain and output registers. The counter chain consists of regis-
ters for seconds, minutes, hours, day of week, day of month, month and year. The RTC is capable of
processing leap years. Each counter has its own output register. Whenever the MPU reads the seconds
register, all other output registers are automatically updated. Since the RTC clock (RTCLK) is not cohe-
rent to the MPU clock, the MPU must read the seconds register until two consecutive reads are the same
(this requires either 2 or 3 reads). At this point, all RTC output registers will have the correct time. Re-
gardless of the MPU clock speed, RTC reads require one wait state.
RTC time is set by writing to the registers RTC_SEC through RTC_YR. Each write operation must be pre-
ceded by a write operation to the WE register in I/O RAM. The value written to the WE register is unim-
portant.
Time adjustments are written to the RTCA_ADJ, PREG and QREG registers. Updates to PREG and QREG
must occur after the one second interrupt and must be finished before reaching the next one second
boundary. The new values are loaded into the counters at the next one second boundary.
PREG and QREG are separate registers in the device hardware, but the bits are 16-bit contiguous so the
MPU firmware can treat them as a single register. A single binary number can be calculated and then
loaded into them at the same time.
The 71M6531D/F and 71M6532D/F have two rate adjustment mechanisms. The first is an analog rate
adjustment, using RTCA_ADJ[6:0], which trims the crystal load capacitance. Setting RTCA_ADJ[6:0] to 00
minimizes the load capacitance, maximizing the oscillator frequency. Setting RTCA_ADJ[6:0] to 0x7F
maximizes the load capacitance, minimizing the oscillator frequency. The adjustable capacitance is ap-
proximately:
RTCA_ ADJ
CADJ
=
⋅16.5pF
128
The maximum adjustment range is approximately-12 ppm to +22ppm. The precise amount of adjustment
will depend on the crystal properties. The adjustment may occur at any time and the resulting clock fre-
quency can be measured over a one-second interval.
The second rate adjustment is a digital rate adjust using PREG and QREG, which can be used to adjust
the clock rate up to ± 988 ppm, with a resolution of 1.9 ppm. Updates must occur after a one second in-
terrupt and must finish before the next one second boundary. The rate adjustment will be implemented
starting at the next one second boundary. Since the LSB results in an adjustment every four seconds,
the frequency should be measured over an interval that is a multiple of four seconds.
To adjust the clock rate using the digital rate adjust, the appropriate values must be written to PREG[16:0]
and QREG[1:0]. The default frequency is 32,768 RTCLK cycles per second. To shift the clock frequency
by ∆ ppm, calculate PREG and QREG using the following equation:
32768⋅8
1+ ∆ ⋅10−6
4⋅ PREG + QREG = floor
+ 0.5
38
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