FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
1.2.2 Input Multiplexer
The input multiplexer supports up to four input signals that are applied to pins IA (IAP/IAN), VA, IB
(IBP/IBN), and VB of the device. Additionally, using the alternate multiplexer selection, it has the ability to
select temperature and the battery voltage. The multiplexer can be operated in two modes:
•
•
During a normal multiplexer cycle, the signals from the IA (IAP/IAN), IB (IBP/IBN), VA and VB pins
are selected.
During the alternate multiplexer cycle, the temperature signal (TEMP) and the battery monitor are
selected, along with some of the voltage and/or current signal sources shown in Table 1. To prevent
unnecessary drainage on the battery, the battery monitor is only active when enabled with the BME
bit (0x2020[6]) in the I/O RAM.
The alternate multiplexer cycles are usually performed infrequently (every second or so) by the MPU. In
order to prevent disruption of the voltage tracking PLL and voltage allpass networks, VA is not replaced in
the ALT selections. Table 1 details the regular and alternative multiplexer sequences. The computation
engine (CE) fills in missing samples due to an ALT multiplexer sequence.
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles
Regular Slot
Typical Selections
Alternate Slot
Typical Selections
Time Slot
Register
Register
RAM Ad-
dress
Signal for
ADC
RAM Ad-
dress
Signal for
ADC
0
1
SLOT0_SEL
SLOT1_SEL
SLOT2_SEL
SLOT3_SEL
SLOT4_SEL
SLOT5_SEL
SLOT6_SEL
SLOT7_SEL
SLOT8_SEL
SLOT9_SEL
0
1
2
3
--
--
--
–
–
–
IA
VB
IB
VA
--
SLOT0_ALTSEL
SLOT1_ALTSEL
SLOT2_ALTSEL
SLOT3_ALTSEL
SLOT4_ALTSEL
SLOT5_ALTSEL
SLOT6_ALTSEL
SLOT7_ALTSEL
SLOT8_ALTSEL
SLOT9_ALTSEL
A
1
TEMP
VB
2
B
3
VBAT
3
VA
--
--
--
–
--
--
--
--
--
--
--
--
--
–
--
--
–
–
–
–
–
–
–
The sequence of sampled channels is fully programmable using I/O RAM registers. SLOTn_SEL selects
the input for the nth state in a standard multiplexer frame, while SLOTn_ALTSEL selects the input for the
nth state in an alternate multiplexer frame. The states shown in Table 1 are examples for possible multip-
lexer state sequences.
In a typical application, IA (IAN/IAP) and IB (IBN/IBP) are connected to current transformers that sense
the current on each phase of the line voltage. VA and VB are typically connected to voltage sensors
through resistor dividers.
The multiplexer control circuit (MUX_CTRL signal) controls multiplexer advance, FIR initiation and VREF
chopping. Additionally, MUX_CTRL launches each pass through the CE program. Conceptually,
MUX_CTRL is clocked by CK32, the 32768 Hz clock from the PLL block. The behavior of MUX_CTRL is
governed by MUX_ALT, EQU, CHOP_E and MUX_DIV.
The MUX_ALT bit requests an alternative multiplexer frame. The bit may be asserted on any MPU cycle
and may be subsequently de-asserted on any cycle including the next one. A rising edge on MUX_ALT
will cause MUX_CTRL to wait until the next multiplexer frame and implement a single alternate multiplex-
er frame.
Another control input to the MUX is MUX_DIV. These four bits can request from 1 to 10 multiplexer states
per frame. The multiplexer always starts at the beginning of its list and proceeds until the number of
states defined by MUX_DIV have been converted.
v1.2
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