71M6521DE/71M6521FE
Energy Meter IC
DATASHEET
JANUARY 2008
PERFORMANCE SPECIFICATIONS
INPUT LOGIC LEVELS
PARAMETER
CONDITION
MIN
2
TYP
MAX
UNIT
V
V
Digital high-level input voltage†, VIH
Digital low-level input voltage†, VIL
Input pull-up current, IIL
E_RXTX,
0.8
VIN=0V, ICE_E=1
10
10
-1
100
100
1
µA
µA
µA
E_RST, CKTEST
Other digital inputs
Input pull down current, IIH
ICE_E
0
VIN=V3P3D
10
-1
-1
100
1
1
µA
µA
µA
PB
0
0
Other digital inputs
†In battery powered modes, digital inputs should be below 0.3V or above 2.5V to minimize battery current.
OUTPUT LOGIC LEVELS
PARAMETER
CONDITION
ILOAD = 1mA
MIN
V3P3D
–0.4
V3P3D-
0.6
TYP
MAX
UNIT
V
Digital high-level output voltage VOH
ILOAD = 15mA
ILOAD = 1mA
V
0
0.4
0.8
0.4
0.7
V
V
V
V
Digital low-level output voltage VOL
I
LOAD = 15mA
OPT_TX VOH (V3P3D-OPT_TX)
OPT_TX VOL
ISOURCE=1mA
ISINK=20mA
POWER-FAULT COMPARATOR
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Offset Voltage
V1-VBIAS
-20
+15
mV
Hysteresis Current
V1
Response Time
V1
Vin = VBIAS - 100mV
+100mV overdrive
0.8
2
1.2
10
μA
μs
5
WDT Disable Threshold (V1-V3P3A)
-400
-10
mV
BATTERY MONITOR
BME=1
PARAMETER
Load Resistor
CONDITION
MIN
27
TYP
45
MAX
63
UNIT
kΩ
FIR_LEN=0
FIR_LEN=1
LSB Value - does not include the 9-bit left
shift at CE input.
Offset Error
-6.0
-2.6
-200
-5.4
-2.3
-72
-4.9
-2.0
+100
μV
μV
mV
Page: 88 of 101
© 2005-2008 TERIDIAN Semiconductor Corporation
v1.0
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
