71M6521BE
Energy Meter IC
DATA SHEET
JANUARY 2008
In a typical application, IA and IB are connected to current transformers that sense the current on each phase of the line
voltage. VA is typically connected to a voltage sensor (resistor divider).
The multiplexer control circuit handles the setting of the multiplexer. The function of the multiplexer control circuit is governed
by the I/O RAM registers MUX_ALT, MUX_DIV and EQU. MUX_DIV controls the number of samples per cycle. It can request 2,
3, or 4 multiplexer states per cycle. Multiplexer states above 4 are reserved and must not be used. The multiplexer always
starts at the beginning of its list and proceeds until MUX_DIV states have been converted.
The MUX_ALT bit requests an alternative multiplexer frame. The bit may be asserted on any MPU cycle and may be
subsequently de-asserted on any cycle including the next one. A rising edge on MUX_ALT will cause the multiplexer control
circuit to wait until the next multiplexer cycle and implement a single alternate cycle.
The multiplexer control circuit also controls the FIR filter initiation and the chopping of the ADC reference voltage, VREF. The
multiplexer control circuits clocked by CK32, the 32768Hz clock from the PLL block, and launches each pass through the CE
program.
A/D Converter (ADC)
A single delta-sigma A/D converter digitizes the voltage and current inputs to the 71M6521BE. The resolution of the ADC is
programmable using the FIR_LEN register as shown in the I/O RAM section. ADC resolution can be selected to be 21 bits
(FIR_LEN=0), or 22 bits (FIR_LEN=1). Conversion time is two cycles of CK32 with FIR_LEN = 0 and three cycles with FIR_LEN
= 1.
In order to provide the maximum resolution, the ADC should be operated with FIR_LEN = 1. Accuracy and timing
specifications in this data sheet are based on FIR_LEN = 1.
Initiation of each ADC conversion is controlled by the multiplexer control circuit as described previously. At the end of each
ADC conversion, the FIR filter output data is stored into the CE DRAM location determined by the multiplexer selection.
FIR Filter
The finite impulse response filter is an integral part of the ADC and it is optimized for use with the multiplexer. The purpose of
the FIR filter is to decimate the ADC output to the desired resolution. At the end of each ADC conversion, the output data is
stored into the fixed CE DRAM location determined by the multiplexer selection. FIR data is stored LSB justified, but shifted left
by nine bits.
Voltage References
The device includes an on-chip precision bandgap voltage reference that incorporates auto-zero techniques. The reference is
trimmed to minimize errors caused by component mismatch and drift. The result is a voltage output with a predictable
temperature coefficient.
The amplifier within the reference is chopper stabilized, i.e. the polarity can be switched by the MPU using the I/O RAM
register CHOP_E (0x2002[5:4]). The two bits in the CHOP_E register enable the MPU to operate the chopper circuit in regular
or inverted operation, or in “toggling” mode. When the chopper circuit is toggled in between multiplexer cycles, DC offsets on
the measured signals will automatically be averaged out.
The general topology of a chopped amplifier is given in Figure 2.
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