71M6515H
Energy Meter IC
DATA SHEET
MARCH 2008
Timing
The fundamental factor for all timing considerations is SUM_CYCLES, which determines the length of the accumulation interval
for the 71M6515H per the equation:
SUM _CYCLES ⋅42
τ =
2520.6Hz
The default setting for SUM_CYCLES is 60, which yields an accumulation interval close to 1,000ms. A conservative minimum
number for SUM_CYCLES is 24, which yields an accumulation interval close to 400ms. Both calculations by the post-processor
in the 71M6515H and the communication between 71M6515H and the host have to be completed within the accumulation
interval. If an accumulation interval has passed, and the energy values have not been read by the host, they are lost forever.
In order to analyze the timing of the communication between the 71M6515H and the host, it is useful to know the basic timing
requirements of the post-processor of the 71M6515H. Some timing parameters are listed in Table 8.
CE_ONLY
VAh Calculation
Resulting Calculation Time
Vector method:
VAh = Wh2 +VARh2
Disabled
350ms
Disabled
Enabled
Vrms*Irms method
X
80ms
40ms
Table 8: Post-processor Timing
As can be seen in Table 8, the calculation time can be greatly reduced if the VAh values are calculated using the method of
multiplying Vrms by Irms (by resetting bit 0 in the CONFIG register), which is less accurate at low currents.
Further improvement can be achieved by disabling the post-processor using the CE_ONLY bit in the CONFIG register. This is
possible for applications where the registers IPHASE, IRMS, VAh and VRMS are not required.
It becomes clear now that the minimum value of 24 for SUM_CYCLES, equivalent to a 400ms accumulation interval, accom-
modates the worst-case scenario, using the vector method, which requires 350ms post-processing time. This setting leaves
around 50ms for the communication to take place between the 71M6515 and the host. If the simpler Irms*Vrms method is
chosen for VAh, a lower value can be selected for SUM_CYCLES.
Lower values for SUM_CYCLES, for example 12, yielding a 200ms accumulation interval, are possible, leaving still 120ms for
host communications, as long as the Vrms*Irms method for VAh is used.
Some other timing parameters are listed in Table 9.
Parameter
Value
Comment
Time from power-up to UART being functional
Time from HW reset to UART being functional
370ms ±10%
370ms ±10%
Soft reset = RESET bit in CONFIG register
is set high.
245ms ±10%
Time from soft reset to UART being functional
UARTCSZ is polled just before the
71M6515H checks its data buffer for a
command. This means that the command
latency specified in the Electrical Specifi-
cations section also applies to the
UARTCSZ pin.
Time from UARTCSZ pin low to UART being functional
20ms
Table 9: UART Timing Parameters
Page: 54 of 57
© 2005-2008 TERIDIAN Semiconductor Corporation
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