71M6515H
Energy Meter IC
DATA SHEET
MARCH 2008
SSI (0x22)
This register controls the function of the Serial Synchronous Interface (SSI). The function of the SSI is described in the
Internal Resources section of this data sheet. If the SSI is enabled (bit 23, SSI_EN, in the SSI register), a block of CNT words
starting at the address BEG will be transmitted each 397µs.
Bits 7-0: These bits (CNT) select the number of CE RAM address locations to be transmitted. The value in CNT must be >=
0.
Bits 15-8: These bits (BEG) define the start address of the transfer region of the CE data RAM address.
Bit 16: This bit must be set to zero.
Bit 17: This bit must be set to zero.
Bit 18: This bit (SSI_FPOL) defines the polarity of the SFR pulse signal (0: positive, 1: negative).
Bits 20-19: These bits (SSI_FSIZE) define the frame pulse format as follows:
SSI_FSIZE
Bit 20
Bit 19
SSI Frame Pulse Format
Once at beginning of SSI sequence
Every 8 bits
0
0
1
1
0
1
0
1
0
1
2
3
Every 16 bits
Every 32 bits
Bit 21: This bit (SSI_CGATE) enables the clock to be gated. When low, the SSCLK signal is active continuously, when high,
the SSCLK signal is held low when no data is being transferred.
Bit 22: This bit (SSI_10M) defines the speed of the SSCLK signal: 0: 5MHz, 1: 10MHz.
Bit 23: This bit (SSI_EN), when set to 1, enables the SSI interface.
Registers Used for I/O Control
D_CONFIG (0x1A)
This register holds three bytes that are used to manipulate the DIO pins of the 71M6515H.
Bits 7-0: These bits (DIO_VALUE) form the data register for the DIO pins D0 through D7. When a byte is written to
DIO_VALUE, the pins configured as outputs (using the D_DIR register) will change their state accordingly. Pins configured
as inputs will ignore the byte written to DIO_VALUE.
Reading DIO_VALUE will return a byte that reflects the state of all pins regardless whether they are configured as inputs or
outputs.
Bits 15-8: These bits are not used
Bits 23-16: These bits (D_DIR) define the data direction. Bit 0 controls the D0 pin, bit 7 controls the D7 pin. Setting the bit
corresponding to a pin to 1 makes the pin an output, clearing it to 0 makes it an input.
Bits 31-24: These bits (DIO_INT_CTRL) form a mask enabling the DEDGE interrupt (bit 9 of the STATUS word register). Bit
8 controls the D0 pin, bit 15 controls the D7 pin. Setting the bit corresponding to a pin to 1 enables the DEDGE interrupt,
clearing the bit disables the interrupt. If the bit in DIO_INT_CTRL is set and a transition from high to low or from low to high
occurs, the DEDGE interrupt bit in the STATUS word register will be set in the following accumulation interval.
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