71M6513/71M6513H
3-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
SEPTEMBER 2011
Note 3: After a reset from an in-circuit emulator, the IE_XFER flag may not be cleared because the CE may continue to run.
The flags for the RTC_1SEC and the XFER_BUSY interrupts are located in the WDI SFR (address 0xE8).
Enable Bit
EX0
Description
Flag Bit
IE0
Description
Enable external interrupt 0
Enable external interrupt 1
Enable external interrupt 2
Enable external interrupt 3
Enable external interrupt 4
Enable external interrupt 5
Enable external interrupt 6
Enable XFER_BUSY interrupt
Enable RTC_1SEC interrupt
External interrupt 0 flag
External interrupt 1 flag
External interrupt 2 flag
External interrupt 3 flag
External interrupt 4 flag
External interrupt 5 flag
External interrupt 6 flag
XFER_BUSY interrupt flag
RTC_1SEC interrupt flag
EX1
IE1
EX2
IEX2
EX3
IEX3
EX4
IEX4
EX5
IEX5
EX6
IEX6
EX_XFER
EX_RTC
IE_XFER
IE_RTC
Table 44: Control Bits for External Interrupts
Interrupt Priority Level Structure
All interrupt sources are combined in groups, as shown in Table 45:
Group
0
1
2
3
4
5
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial channel 0 interrupt
-
Serial channel 1 interrupt
-
-
-
-
-
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
Table 45: Priority Level Groups
Each group of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one bit in
the special function register IP0 and one in IP1. If requests of the same priority level are received simultaneously, an internal
polling sequence as per Table 49 determines which request is serviced first.
IEN enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own flag bit that is set by
the interrupt hardware and is reset automatically by the MPU interrupt handler (0 through 5). XFER_BUSY and RTC_1SEC,
which are OR-ed together, have their own enable and flag bits in addition to the interrupt 6 enable and flag bits (see Table 44),
and these interrupts must be cleared by the MPU software.
An overview of the interrupt structure is shown in Figure 7.
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