71M6513/71M6513H
3-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
AUGUST 2011
Bit
Symbol
Function
IRCON.7
IRCON.6
IRCON.5
IRCON.4
IRCON.3
IRCON.2
IRCON.1
IRCON.0
-
-
IEX6
IEX5
IEX4
IEX3
IEX2
-
External interrupt 6 edge flag
External interrupt 5 edge flag
External interrupt 4 edge flag
External interrupt 3 edge flag
External interrupt 2 edge flag
Table 42: The IRCON Bit Functions
Note: Only TF0 and TF1 (timer 0 and timer 1 overflow flag) will be automatically cleared by hardware when the service routine
is called (Signals T0ACK and T1ACK – port ISR – active high when the service routine is called).
External Interrupts
The external interrupts are connected as shown in Table 43. The polarity of interrupts 2 and 3 is programmable in the MPU.
Interrupts 2 and 3 should be programmed for falling sensitivity. The generic 8051 MPU literature states that interrupts 4
through 6 are defined as rising edge sensitive. Thus, the hardware signals attached to interrupts 5 and 6 are inverted to
achieve the edge polarity shown in Table 43.
SFR (special function register) enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has
its own flag bit that is set by the interrupt hardware and is reset automatically by the MPU interrupt handler (0 through 5).
XFER_BUSY and RTC_1SEC, which are OR-ed together, have their own enable and flag bits in addition to the interrupt 6
enable and flag bits (see Table 44), and these interrupts must be cleared by the MPU software.
External
Interrupt
Connection
Polarity
Flag Reset
0
1
2
3
4
5
6
Digital I/O High Priority
Digital I/O Low Priority
Comparator 2 or 3
CE_BUSY
see DIO_Rx
see DIO_Rx
falling
automatic
automatic
automatic
automatic
automatic
automatic
manual
falling
Comparator 2 or 3
EEPROM busy
rising
falling
XFER_BUSY OR RTC_1SEC
falling
Table 43: External MPU Interrupts
Interrupt 6 is edge-sensitive. The RTC_1SEC interrupt from the RTC and the XFER_BUSY interrupt from the CE are com-
bined using a logic OR function and the result is routed into interrupt 6. Therefore, both flags must be cleared at least once
during initialization, and both flags must always be cleared before exiting the interrupt service routine (ISR) for interrupt 6.
Note 1: If clearing of both flags is not performed, then no edge can occur to trigger interrupt 6 later resulting in the ISR for the
XFER_BUSY ceasing to run.
Note 2: Clearing both flags reliably requires some care. Either flag can be set by hardware while interrupt 6 code is running on
behalf of the other interrupt. In this situation, the unprocessed interrupt can create a lockout condition similar to the one in note
1. To prevent this lockout one must always process both interrupt flags in the same service routine.
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