71M6513/71M6513H
3-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
SEPTEMBER 2011
Watt & VAR Formula
EQU
Inputs used from MUX se-
quence
Inputs used from alternate MUX
sequence
Mux State:
Mux State:
0
1
2
3
4
5
0
1
2
3
4
5
VA IA
(1 element, 2W 1ø)
0
1
2
3
4
5
IA
VA
IB VB IC VC
IB VB IC VC
IB VB IC VC
IB VB IC VC
IB VB IC VC
IB VB IC VC
TEMP VA V3 VC
TEMP VA IB V3
TEMP VA V3 VB
IC
VC
VA(IA-IB)/2
(1 element, 3W 1ø)
IA
IA
IA
IA
IA
VA
VA
VA
VA
VA
VC
VC
IC
VC
VC
VC
VC
VC
VA IA + VB IB
(2 element, 3W 3 øDelta)
VA (IA - IB)/2 + VC IC
(2 element, 4W 3ø Delta)
TEMP VA IB
TEMP VA IB
V3
V3
VA(IA-IB)/2 + VB(IC-IB)/2
(2 element, 4W 3ø Wye)
IC
VA IA + VB IB + VC IC
(3 element, 4W 3ø Wye)
TEMP VA V3 VB
IC
Table 3: Standard Meter Equations (inputs shown gray are scanned but not used for calculation)
Pulse Generator
The CE contains two pulse generators which create low jitter pulses at a rate set by the CE DRAM registers APULSEW*WRATE
and APULSER*WRATE if EXT_PULSE (a CE input variable in CE DRAM) is 15. This mode puts the MPU in control of pulse
generation by placing values into the APULSEW and APULSER registers (“external pulse generation”).
If EXT_PULSE is 0, APULSEW is replaced with WSUM_X and APULSER is replaced with VARSUM_X. In this mode, the CE
generates pulse based on its internal computation of WSUM_X and VARSUM_X, the signed sums of energy from all three
elements (“internal pulse generation”).
The DIO_PV and DIO_PW bits as described in the Digital I/O section can be programmed to route WPULSE and VARPULSE
to the output pins DIO6 and DIO7 respectively. DIO6 and DIO7 can be configured to generate interrupts, which can be useful
for pulse counting by the MPU (see On-Chip Resources, DIO Ports section).
Real-Time Monitor
The CE contains a Real Time Monitor (RTM), which can be programmed to monitor four selectable CE RAM locations at full
sample rate. The four monitored locations are serially output to the TMUXOUT pin via the digital output multiplexer at the
beginning of each CE code pass (see the Test Ports Section for details)
CE Functional Overview
The ADC processes one sample per channel per multiplexer cycle. Figure 4 shows the timing of the six samples taken during
one multiplexer cycle.
The number of samples processed during one accumulation cycle is controlled by the I/O RAM registers PRE_SAMPS
(0x2001[7:6]) and SUM_CYCLES (0x2001[5:0]). The integration time for each energy output is
PRE_SAMPS * SUM_CYCLES / 2520.6, where 2520.6 is the sample rate [Hz]
For example, PRE_SAMPS = 42 and SUM_CYCLES = 50 will establish 2100 samples per accumulation cycle. PRE_SAMPS = 100
and SUM_CYCLES = 21 will result in the exact same accumulation cycle of 2100 samples or 833ms. After an accumulation
cycle is completed, the XFER_BUSY interrupt signals to the MPU that accumulated data are available.
© 2005-2011 Teridian Semiconductor Corporation
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